--------------------------------------------------------------------------------Xilinx TRACE, Version M1.4.12Copyright (c) 1995-1997 Xilinx, Inc.  All rights reserved.Design file:              binary.ncdPhysical constraint file: binary.pcfDevice,speed:             xc4005e,-2 (x1_0.86  PRELIMINARY)Report level:             summary report--------------------------------------------------------------------------------WARNING:bastw:172 - No timing constraints found, doing advanced analysis with   offsets.================================================================================Timing constraint: Default period analysis for net n128 54 items analyzed, 0 timing errors detected. Minimum period is  13.887ns.--------------------------------------------------------------------------------================================================================================Timing constraint: Default OFFSET IN BEFORE analysis for clock "n128" 25 items analyzed, 0 timing errors detected. Minimum allowable offset is   9.423ns.--------------------------------------------------------------------------------================================================================================Timing constraint: Default OFFSET OUT AFTER analysis for clock "n128" 9 items analyzed, 0 timing errors detected. Maximum allowable offset is  19.062ns.--------------------------------------------------------------------------------================================================================================Timing constraint: Default path analysis 12 items analyzed, 0 timing errors detected. Maximum delay is  15.114ns.--------------------------------------------------------------------------------All constraints were met.Timing summary:---------------Timing errors: 0  Score: 0Constraints cover 95 paths, 0 nets, and 70 connections (100.0% coverage)Design statistics:   Minimum period:  13.887ns (Maximum frequency:  72.010MHz)   Maximum combinational path delay:  15.114ns   Minimum input arrival time before clock:   9.423ns   Maximum output required time before clock:  19.062nsAnalysis completed Tue Jan  6 18:06:52 1998--------------------------------------------------------------------------------