// Xilinx Verilog produced by program ngd2ver, Version M1.4.12// Date: Tue Jan  6 18:00:56 1998// Design file: time_sim.nga// Device: 4005epc84-2`timescale 1 ns/1 ps`uselib dir=/home/zeppelin2/tech_apps/m1_4.12/verilog/data libext=.vmd  module one_hot (CLOCK, RESET, A, B, C, D, E, SINGLE, MULTI, CONTIG);    input CLOCK;    input RESET;    input A;    input B;    input C;    input D;    input E;    output SINGLE;    output MULTI;    output CONTIG;    wire n135, n136, n137, n138, n139, n140, n141, n230, n231, n232, n194, n192    , n193, n195, n172, n196, n197, n175, n198, n171, n202, n176, n201, n200,     n199, n203, n205, n204, n206, n213, n210, n212, n207, n209, n208, n211, n214    , n215, n217, n216, n218, n219, n223, n221, n220, n222, n224, n229, n228,     n225, n226, n227, \U108/$1I20_GTS_TRI , \U109/$1I20_GTS_TRI ,     \U110/$1I20_GTS_TRI , \CS_reg[3]/$1I13_GSR_OR , \CS_reg[5]/$1I13_GSR_OR ,     \CS_reg[2]/$1I13_GSR_OR , \CS_reg[6]/$1I13_GSR_OR , \CS_reg[4]/$1I13_GSR_OR     , \CS_reg[1]/$1I13_GSR_OR , \U101/clkio_bufsig , \U111/2_0 , \U120/2_0 ,     \U126/2_0 , \U130/2_0 , \U130/2_1 , \U133/2_0 , \U144/2_0 , \U144/2_1 ,     \U152/2_0 , \U152/2_1 , \U154/2_0 , \U154/2_1 , U112_2_INV, U114_2_INV,     U116_2_INV, U118_2_INV, U121_2_INV, U122_2_INV, U124_2_INV, U128_2_INV,     U131_2_INV, U132_2_INV, U134_2_INV, U137_2_INV, U140_2_INV, U142_2_INV,     U147_2_INV, U149_2_INV, \U154/n171_2_INV , \U108/$1I20_GTS_TRI_2_INV ,     \U109/$1I20_GTS_TRI_2_INV , \U110/$1I20_GTS_TRI_2_INV , GND, VCC;    wire [6:1] CS;    `ifdef GSR_SIGNAL      wire GSR = `GSR_SIGNAL ;    `else      wire GSR ;    `endif    `ifdef GTS_SIGNAL      wire GTS = `GTS_SIGNAL ;    `else      wire GTS ;    `endif    initial $sdf_annotate("time_sim.sdf");    X_BUF U102 (.IN (RESET), .OUT (n136));    X_BUF U103 (.IN (A), .OUT (n137));    X_BUF U104 (.IN (B), .OUT (n138));    X_BUF U105 (.IN (C), .OUT (n139));    X_BUF U106 (.IN (D), .OUT (n140));    X_BUF U107 (.IN (E), .OUT (n141));    X_AND2 U112 (.IN0 (n192), .IN1 (n195), .OUT (U112_2_INV));    X_INV U113 (.IN (CS[4]), .OUT (n192));    X_AND2 U114 (.IN0 (n193), .IN1 (n194), .OUT (U114_2_INV));    X_XOR2 U115 (.IN0 (CS[1]), .IN1 (CS[3]), .OUT (n195));    X_OR2 U116 (.IN0 (n230), .IN1 (CS[6]), .OUT (U116_2_INV));    X_INV U117 (.IN (CS[3]), .OUT (n196));    X_OR2 U118 (.IN0 (n175), .IN1 (n196), .OUT (U118_2_INV));    X_AND2 U119 (.IN0 (n175), .IN1 (n171), .OUT (n198));    X_AND2 U121 (.IN0 (n140), .IN1 (CS[1]), .OUT (U121_2_INV));    X_AND2 U122 (.IN0 (n199), .IN1 (CS[2]), .OUT (U122_2_INV));    X_OR2 U123 (.IN0 (n137), .IN1 (n140), .OUT (n199));    X_AND2 U124 (.IN0 (n200), .IN1 (n201), .OUT (U124_2_INV));    X_INV U125 (.IN (n139), .OUT (n203));    X_INV U127 (.IN (n204), .OUT (n205));    X_AND2 U128 (.IN0 (n230), .IN1 (n141), .OUT (U128_2_INV));    X_OR2 U129 (.IN0 (CS[4]), .IN1 (n205), .OUT (n206));    X_AND2 U131 (.IN0 (n210), .IN1 (n207), .OUT (U131_2_INV));    X_AND2 U132 (.IN0 (n209), .IN1 (n208), .OUT (U132_2_INV));    X_AND2 U134 (.IN0 (n211), .IN1 (n214), .OUT (U134_2_INV));    X_INV U135 (.IN (CS[6]), .OUT (n210));    X_INV U136 (.IN (n230), .OUT (n211));    X_AND2 U137 (.IN0 (n212), .IN1 (n213), .OUT (U137_2_INV));    X_XOR2 U138 (.IN0 (CS[2]), .IN1 (CS[3]), .OUT (n214));    X_INV U139 (.IN (n137), .OUT (n215));    X_OR2 U140 (.IN0 (CS[1]), .IN1 (n216), .OUT (U140_2_INV));    X_AND2 U141 (.IN0 (n215), .IN1 (CS[2]), .OUT (n216));    X_OR2 U142 (.IN0 (n217), .IN1 (n140), .OUT (U142_2_INV));    X_INV U143 (.IN (n139), .OUT (n219));    X_INV U145 (.IN (n220), .OUT (n221));    X_OR2 U146 (.IN0 (CS[6]), .IN1 (n230), .OUT (n220));    X_OR2 U147 (.IN0 (n221), .IN1 (n141), .OUT (U147_2_INV));    X_INV U148 (.IN (n171), .OUT (n224));    X_OR2 U149 (.IN0 (n228), .IN1 (n224), .OUT (U149_2_INV));    X_INV U150 (.IN (n139), .OUT (n225));    X_INV U151 (.IN (n137), .OUT (n226));    X_INV U153 (.IN (n172), .OUT (n227));    X_IPAD CLOCK_PAD (.PAD (CLOCK));    X_IPAD RESET_PAD (.PAD (RESET));    X_IPAD A_PAD (.PAD (A));    X_IPAD B_PAD (.PAD (B));    X_IPAD C_PAD (.PAD (C));    X_IPAD D_PAD (.PAD (D));    X_IPAD E_PAD (.PAD (E));    X_OPAD SINGLE_PAD (.PAD (SINGLE));    X_OPAD MULTI_PAD (.PAD (MULTI));    X_OPAD CONTIG_PAD (.PAD (CONTIG));    X_BUF \U108/$1I20  (.IN (n230), .OUT (\U108/$1I20_GTS_TRI ));    X_TRI \U108/$1I20_GTS_TRI_121  (.IN (\U108/$1I20_GTS_TRI ), .OUT (SINGLE),     .CTL (\U108/$1I20_GTS_TRI_2_INV ));    X_BUF \U109/$1I20  (.IN (n231), .OUT (\U109/$1I20_GTS_TRI ));    X_TRI \U109/$1I20_GTS_TRI_122  (.IN (\U109/$1I20_GTS_TRI ), .OUT (MULTI),     .CTL (\U109/$1I20_GTS_TRI_2_INV ));    X_BUF \U110/$1I20  (.IN (n232), .OUT (\U110/$1I20_GTS_TRI ));    X_TRI \U110/$1I20_GTS_TRI_123  (.IN (\U110/$1I20_GTS_TRI ), .OUT (CONTIG),     .CTL (\U110/$1I20_GTS_TRI_2_INV ));    X_FF \CS_reg<3>/$1I13  (.IN (n202), .CLK (n135), .CE (VCC), .SET (GND),     .RST (\CS_reg[3]/$1I13_GSR_OR ), .OUT (CS[3]));    X_OR2 \CS_reg<3>/$1I13_GSR_OR_115  (.IN0 (n136), .IN1 (GSR), .OUT     (\CS_reg[3]/$1I13_GSR_OR ));    X_FF \CS_reg<5>/$1I13  (.IN (n206), .CLK (n135), .CE (VCC), .SET (GND),     .RST (\CS_reg[5]/$1I13_GSR_OR ), .OUT (n230));    X_OR2 \CS_reg<5>/$1I13_GSR_OR_116  (.IN0 (n136), .IN1 (GSR), .OUT     (\CS_reg[5]/$1I13_GSR_OR ));    X_FF \CS_reg<2>/$1I13  (.IN (n218), .CLK (n135), .CE (VCC), .SET (GND),     .RST (\CS_reg[2]/$1I13_GSR_OR ), .OUT (CS[2]));    X_OR2 \CS_reg<2>/$1I13_GSR_OR_117  (.IN0 (n136), .IN1 (GSR), .OUT     (\CS_reg[2]/$1I13_GSR_OR ));    X_FF \CS_reg<6>/$1I13  (.IN (n222), .CLK (n135), .CE (VCC), .SET (GND),     .RST (\CS_reg[6]/$1I13_GSR_OR ), .OUT (CS[6]));    X_OR2 \CS_reg<6>/$1I13_GSR_OR_118  (.IN0 (n136), .IN1 (GSR), .OUT     (\CS_reg[6]/$1I13_GSR_OR ));    X_FF \CS_reg<4>/$1I13  (.IN (n223), .CLK (n135), .CE (VCC), .SET (GND),     .RST (\CS_reg[4]/$1I13_GSR_OR ), .OUT (CS[4]));    X_OR2 \CS_reg<4>/$1I13_GSR_OR_119  (.IN0 (n136), .IN1 (GSR), .OUT     (\CS_reg[4]/$1I13_GSR_OR ));    X_FF \CS_reg<1>/$1I13  (.IN (n229), .CLK (n135), .CE (VCC), .SET (GND),     .RST (\CS_reg[1]/$1I13_GSR_OR ), .OUT (CS[1]));    X_OR2 \CS_reg<1>/$1I13_GSR_OR_120  (.IN0 (n136), .IN1 (GSR), .OUT     (\CS_reg[1]/$1I13_GSR_OR ));    X_CKBUF \U101/clkbuf  (.IN (\U101/clkio_bufsig ), .OUT (n135));    X_BUF \U101/clkio_buf  (.IN (CLOCK), .OUT (\U101/clkio_bufsig ));    X_OR2 \U111/n194/2_0  (.IN0 (CS[1]), .IN1 (CS[3]), .OUT (\U111/2_0 ));    X_OR2 \U111/n194  (.IN0 (\U111/2_0 ), .IN1 (n192), .OUT (n194));    X_OR2 \U120/n202/2_0  (.IN0 (n198), .IN1 (n197), .OUT (\U120/2_0 ));    X_OR2 \U120/n202  (.IN0 (\U120/2_0 ), .IN1 (n176), .OUT (n202));    X_AND2 \U126/n175/2_0  (.IN0 (n138), .IN1 (n203), .OUT (\U126/2_0 ));    X_AND2 \U126/n175  (.IN0 (\U126/2_0 ), .IN1 (n137), .OUT (n175));    X_OR2 \U130/n213/2_0  (.IN0 (CS[3]), .IN1 (n230), .OUT (\U130/2_0 ));    X_OR2 \U130/n213/2_1  (.IN0 (CS[2]), .IN1 (n210), .OUT (\U130/2_1 ));    X_OR2 \U130/n213  (.IN0 (\U130/2_0 ), .IN1 (\U130/2_1 ), .OUT (n213));    X_OR2 \U133/n208/2_0  (.IN0 (CS[2]), .IN1 (CS[3]), .OUT (\U133/2_0 ));    X_OR2 \U133/n208  (.IN0 (\U133/2_0 ), .IN1 (n211), .OUT (n208));    X_AND2 \U144/n223/2_0  (.IN0 (n137), .IN1 (n138), .OUT (\U144/2_0 ));    X_AND2 \U144/n223/2_1  (.IN0 (CS[3]), .IN1 (n219), .OUT (\U144/2_1 ));    X_AND2 \U144/n223  (.IN0 (\U144/2_0 ), .IN1 (\U144/2_1 ), .OUT (n223));    X_OR2 \U152/n228/2_0  (.IN0 (n226), .IN1 (n138), .OUT (\U152/2_0 ));    X_OR2 \U152/n228/2_1  (.IN0 (n225), .IN1 (CS[2]), .OUT (\U152/2_1 ));    X_OR2 \U152/n228  (.IN0 (\U152/2_0 ), .IN1 (\U152/2_1 ), .OUT (n228));    X_OR2 \U154/n171/2_0  (.IN0 (CS[4]), .IN1 (CS[3]), .OUT (\U154/2_0 ));    X_OR2 \U154/n171/2_1  (.IN0 (CS[1]), .IN1 (n227), .OUT (\U154/2_1 ));    X_OR2 \U154/n171  (.IN0 (\U154/2_0 ), .IN1 (\U154/2_1 ), .OUT     (\U154/n171_2_INV ));    X_INV U112_2_INV_124 (.IN (U112_2_INV), .OUT (n193));    X_INV U114_2_INV_125 (.IN (U114_2_INV), .OUT (n231));    X_INV U116_2_INV_126 (.IN (U116_2_INV), .OUT (n172));    X_INV U118_2_INV_127 (.IN (U118_2_INV), .OUT (n197));    X_INV U121_2_INV_128 (.IN (U121_2_INV), .OUT (n201));    X_INV U122_2_INV_129 (.IN (U122_2_INV), .OUT (n200));    X_INV U124_2_INV_130 (.IN (U124_2_INV), .OUT (n176));    X_INV U128_2_INV_131 (.IN (U128_2_INV), .OUT (n204));    X_INV U131_2_INV_132 (.IN (U131_2_INV), .OUT (n212));    X_INV U132_2_INV_133 (.IN (U132_2_INV), .OUT (n207));    X_INV U134_2_INV_134 (.IN (U134_2_INV), .OUT (n209));    X_INV U137_2_INV_135 (.IN (U137_2_INV), .OUT (n232));    X_INV U140_2_INV_136 (.IN (U140_2_INV), .OUT (n217));    X_INV U142_2_INV_137 (.IN (U142_2_INV), .OUT (n218));    X_INV U147_2_INV_138 (.IN (U147_2_INV), .OUT (n222));    X_INV U149_2_INV_139 (.IN (U149_2_INV), .OUT (n229));    X_INV \U154/n171_2_INV_140  (.IN (\U154/n171_2_INV ), .OUT (n171));    X_INV \U108/$1I20_GTS_TRI_2_INV_141  (.IN (GTS), .OUT     (\U108/$1I20_GTS_TRI_2_INV ));    X_INV \U109/$1I20_GTS_TRI_2_INV_142  (.IN (GTS), .OUT     (\U109/$1I20_GTS_TRI_2_INV ));    X_INV \U110/$1I20_GTS_TRI_2_INV_143  (.IN (GTS), .OUT     (\U110/$1I20_GTS_TRI_2_INV ));    X_ONE VCC_144 (.OUT (VCC));    X_ZERO GND_145 (.OUT (GND));    X_PD NGD2VER_PD_110 (.OUT (GSR) );    X_PD NGD2VER_PD_112 (.OUT (GTS) );  endmodule