// VERILOG TestFixture Template produced by ngd2ver M1.4.12// Design file: time_sim.nga// Date:Tue Jan  6 18:04:23 1998// ATTENTION: This file was created by NGD2VER and may therefore be overwritten// by subsequent runs of NGD2VER. Xilinx recommends that you copy this file to// a new name, or 'paste' this text into another file, to avoid accidental loss// of data.`timescale 1 ns/1 psmodule test;  reg CLOCK;  reg RESET;  reg A;  reg B;  reg C;  reg D;  reg E;  wire SINGLE;  wire MULTI;  wire CONTIG;  reg GSR;  `define GSR_SIGNAL test.GSR  reg GTS;  `define GTS_SIGNAL test.GTS  enum uut ( .CLOCK (CLOCK) , .RESET (RESET) , .A (A) , .B (B) , .C (C) , .D (D) , .E (E) , .SINGLE (SINGLE) , .MULTI (MULTI) , .CONTIG (CONTIG) );  initial begin    $timeformat(-9,3,"ns",12);    $shm_open("time_sim.shm");    $shm_probe("AS");  end  initial begin    $display("           T CRABCDESMC");    $display("           i LE     IUO");    $display("           m OS     NLN");    $display("           e CE     GTT");    $display("             KT     LII");    $display("                    E G");    $monitor("%t",$realtime,, CLOCK, RESET, A, B, C, D, E, SINGLE, MULTI, CONTIG );  end  initial begin      `GSR_SIGNAL = 1;      `GTS_SIGNAL = 0;    #100      `GSR_SIGNAL = 0;      CLOCK = 0 ;      RESET = 0 ;      A = 0 ;      B = 0 ;      C = 0 ;      D = 0 ;      E = 0 ;    #1000 $stop;    // #1000 $finish;  endendmodule