// Xilinx Verilog produced by program ngd2ver, Version M1.4.12// Date: Tue Jan  6 18:04:23 1998// Design file: time_sim.nga// Device: 4005epc84-2`timescale 1 ns/1 ps`uselib dir=/home/zeppelin2/tech_apps/m1_4.12/verilog/data libext=.vmd  module enum (CLOCK, RESET, A, B, C, D, E, SINGLE, MULTI, CONTIG);    input CLOCK;    input RESET;    input A;    input B;    input C;    input D;    input E;    output SINGLE;    output MULTI;    output CONTIG;    wire n174, n175, n176, n177, n178, n179, n180, \U99/n58 , \U99/n57 ,     \U99/n56 , \U99/S2_q , \U99/S5_q , \U99/S4_q , \U99/n28 , \U99/n29 ,     \U99/n13 , \U99/n30 , \U99/S1_q , \U99/n31 , \U99/n14 , \U99/n34 , \U99/n33     , \U99/n32 , \U99/S3_q , \U99/n35 , \U99/n37 , \U99/n36 , \U99/n38 ,     \U99/n40 , \U99/n39 , \U99/S7_q , \U99/n43 , \U99/n41 , \U99/n42 , \U99/n44     , \U99/n46 , \U99/n45 , \U99/n49 , \U99/n47 , \U99/n48 , \U99/n51 ,     \U99/n50 , \U99/n55 , \U99/n54 , \U99/n53 , \U99/n52 ,     \U99/U36/$1I20_GTS_TRI , \U99/U37/$1I20_GTS_TRI , \U99/U38/$1I20_GTS_TRI ,     \U99/S4/$1I13_GSR_OR , \U99/S6/$1I13_GSR_OR , \U99/S5/$1I13_GSR_OR ,     \U99/S7/$1I13_GSR_OR , \U99/S2/$1I13_GSR_OR , \U99/S3/$1I13_GSR_OR ,     \U99/S1/$1I13_GSR_OR , \U113/clkio_bufsig , \U99/U39/2_0 , \U99/U43/2_0 ,     \U99/U49/2_0 , \U99/U53/2_0 , \U99/U58/2_0 , \U99/U58/2_1 , \U99/U64/2_0 ,     \U99/U64/2_1 , \U99/U41_2_INV , \U99/U44_2_INV , \U99/U45_2_INV ,     \U99/U47_2_INV , \U99/U51_2_INV , \U99/U56_2_INV , \U99/U60_2_INV ,     \U99/U62_2_INV , \U99/U66_2_INV , \U99/U68_2_INV , \U99/U53/U99/n56_2_INV ,     \U99/U36/$1I20_GTS_TRI_2_INV , \U99/U37/$1I20_GTS_TRI_2_INV ,     \U99/U38/$1I20_GTS_TRI_2_INV , GND, VCC;    `ifdef GSR_SIGNAL      wire GSR = `GSR_SIGNAL ;    `else      wire GSR ;    `endif    `ifdef GTS_SIGNAL      wire GTS = `GTS_SIGNAL ;    `else      wire GTS ;    `endif    initial $sdf_annotate("time_sim.sdf");    X_BUF U114 (.IN (RESET), .OUT (n175));    X_BUF U115 (.IN (A), .OUT (n176));    X_BUF U116 (.IN (B), .OUT (n177));    X_BUF U117 (.IN (C), .OUT (n178));    X_BUF U118 (.IN (D), .OUT (n179));    X_BUF U119 (.IN (E), .OUT (n180));    X_INV \U99/U40  (.IN (\U99/S4_q ), .OUT (\U99/n28 ));    X_OR2 \U99/U41  (.IN0 (\U99/n13 ), .IN1 (\U99/n28 ), .OUT (\U99/U41_2_INV )    );    X_AND2 \U99/U42  (.IN0 (\U99/n13 ), .IN1 (\U99/S1_q ), .OUT (\U99/n30 ));    X_AND2 \U99/U44  (.IN0 (n179), .IN1 (\U99/S2_q ), .OUT (\U99/U44_2_INV ));    X_AND2 \U99/U45  (.IN0 (\U99/n32 ), .IN1 (\U99/S3_q ), .OUT     (\U99/U45_2_INV ));    X_OR2 \U99/U46  (.IN0 (n176), .IN1 (n179), .OUT (\U99/n32 ));    X_AND2 \U99/U47  (.IN0 (\U99/n33 ), .IN1 (\U99/n34 ), .OUT (\U99/U47_2_INV )    );    X_INV \U99/U48  (.IN (n178), .OUT (\U99/n35 ));    X_INV \U99/U50  (.IN (\U99/n36 ), .OUT (\U99/n37 ));    X_AND2 \U99/U51  (.IN0 (n180), .IN1 (\U99/n58 ), .OUT (\U99/U51_2_INV ));    X_OR2 \U99/U52  (.IN0 (\U99/S5_q ), .IN1 (\U99/n37 ), .OUT (\U99/n38 ));    X_INV \U99/U54  (.IN (\U99/n39 ), .OUT (\U99/n40 ));    X_OR2 \U99/U55  (.IN0 (\U99/n58 ), .IN1 (\U99/S7_q ), .OUT (\U99/n39 ));    X_OR2 \U99/U56  (.IN0 (\U99/n40 ), .IN1 (n180), .OUT (\U99/U56_2_INV ));    X_INV \U99/U57  (.IN (n178), .OUT (\U99/n41 ));    X_INV \U99/U59  (.IN (n176), .OUT (\U99/n44 ));    X_OR2 \U99/U60  (.IN0 (\U99/S2_q ), .IN1 (\U99/n45 ), .OUT (\U99/U60_2_INV )    );    X_AND2 \U99/U61  (.IN0 (\U99/n44 ), .IN1 (\U99/S3_q ), .OUT (\U99/n45 ));    X_OR2 \U99/U62  (.IN0 (\U99/n46 ), .IN1 (n179), .OUT (\U99/U62_2_INV ));    X_INV \U99/U63  (.IN (n177), .OUT (\U99/n47 ));    X_INV \U99/U65  (.IN (\U99/n50 ), .OUT (\U99/n51 ));    X_AND2 \U99/U66  (.IN0 (n180), .IN1 (\U99/S7_q ), .OUT (\U99/U66_2_INV ));    X_OR2 \U99/U67  (.IN0 (\U99/n54 ), .IN1 (\U99/n51 ), .OUT (\U99/n55 ));    X_AND2 \U99/U68  (.IN0 (n176), .IN1 (\U99/n52 ), .OUT (\U99/U68_2_INV ));    X_XOR2 \U99/U69  (.IN0 (n178), .IN1 (n177), .OUT (\U99/n52 ));    X_AND2 \U99/U70  (.IN0 (\U99/n53 ), .IN1 (\U99/S1_q ), .OUT (\U99/n54 ));    X_IPAD CLOCK_PAD (.PAD (CLOCK));    X_IPAD RESET_PAD (.PAD (RESET));    X_IPAD A_PAD (.PAD (A));    X_IPAD B_PAD (.PAD (B));    X_IPAD C_PAD (.PAD (C));    X_IPAD D_PAD (.PAD (D));    X_IPAD E_PAD (.PAD (E));    X_OPAD SINGLE_PAD (.PAD (SINGLE));    X_OPAD MULTI_PAD (.PAD (MULTI));    X_OPAD CONTIG_PAD (.PAD (CONTIG));    X_BUF \U99/U36/$1I20  (.IN (\U99/n58 ), .OUT (\U99/U36/$1I20_GTS_TRI ));    X_TRI \U99/U36/$1I20_GTS_TRI_93  (.IN (\U99/U36/$1I20_GTS_TRI ), .OUT     (SINGLE), .CTL (\U99/U36/$1I20_GTS_TRI_2_INV ));    X_BUF \U99/U37/$1I20  (.IN (\U99/n57 ), .OUT (\U99/U37/$1I20_GTS_TRI ));    X_TRI \U99/U37/$1I20_GTS_TRI_94  (.IN (\U99/U37/$1I20_GTS_TRI ), .OUT     (MULTI), .CTL (\U99/U37/$1I20_GTS_TRI_2_INV ));    X_BUF \U99/U38/$1I20  (.IN (\U99/n56 ), .OUT (\U99/U38/$1I20_GTS_TRI ));    X_TRI \U99/U38/$1I20_GTS_TRI_95  (.IN (\U99/U38/$1I20_GTS_TRI ), .OUT     (CONTIG), .CTL (\U99/U38/$1I20_GTS_TRI_2_INV ));    X_FF \U99/S4/$1I13  (.IN (\U99/n31 ), .CLK (n174), .CE (VCC), .SET (GND),     .RST (\U99/S4/$1I13_GSR_OR ), .OUT (\U99/S4_q ));    X_OR2 \U99/S4/$1I13_GSR_OR_86  (.IN0 (n175), .IN1 (GSR), .OUT     (\U99/S4/$1I13_GSR_OR ));    X_FF \U99/S6/$1I13  (.IN (\U99/n38 ), .CLK (n174), .CE (VCC), .SET (GND),     .RST (\U99/S6/$1I13_GSR_OR ), .OUT (\U99/n58 ));    X_OR2 \U99/S6/$1I13_GSR_OR_87  (.IN0 (n175), .IN1 (GSR), .OUT     (\U99/S6/$1I13_GSR_OR ));    X_FF \U99/S5/$1I13  (.IN (\U99/n42 ), .CLK (n174), .CE (VCC), .SET (GND),     .RST (\U99/S5/$1I13_GSR_OR ), .OUT (\U99/S5_q ));    X_OR2 \U99/S5/$1I13_GSR_OR_88  (.IN0 (n175), .IN1 (GSR), .OUT     (\U99/S5/$1I13_GSR_OR ));    X_FF \U99/S7/$1I13  (.IN (\U99/n43 ), .CLK (n174), .CE (VCC), .SET (GND),     .RST (\U99/S7/$1I13_GSR_OR ), .OUT (\U99/S7_q ));    X_OR2 \U99/S7/$1I13_GSR_OR_89  (.IN0 (n175), .IN1 (GSR), .OUT     (\U99/S7/$1I13_GSR_OR ));    X_FF \U99/S2/$1I13  (.IN (\U99/n48 ), .CLK (n174), .CE (VCC), .SET (GND),     .RST (\U99/S2/$1I13_GSR_OR ), .OUT (\U99/S2_q ));    X_OR2 \U99/S2/$1I13_GSR_OR_90  (.IN0 (n175), .IN1 (GSR), .OUT     (\U99/S2/$1I13_GSR_OR ));    X_FF \U99/S3/$1I13  (.IN (\U99/n49 ), .CLK (n174), .CE (VCC), .SET (GND),     .RST (\U99/S3/$1I13_GSR_OR ), .OUT (\U99/S3_q ));    X_OR2 \U99/S3/$1I13_GSR_OR_91  (.IN0 (n175), .IN1 (GSR), .OUT     (\U99/S3/$1I13_GSR_OR ));    X_FF \U99/S1/$1I13  (.IN (\U99/n55 ), .CLK (n174), .CE (VCC), .SET     (\U99/S1/$1I13_GSR_OR ), .RST (GND), .OUT (\U99/S1_q ));    X_OR2 \U99/S1/$1I13_GSR_OR_92  (.IN0 (n175), .IN1 (GSR), .OUT     (\U99/S1/$1I13_GSR_OR ));    X_CKBUF \U113/clkbuf  (.IN (\U113/clkio_bufsig ), .OUT (n174));    X_BUF \U113/clkio_buf  (.IN (CLOCK), .OUT (\U113/clkio_bufsig ));    X_OR2 \U99/U39/U99/n57/2_0  (.IN0 (\U99/S4_q ), .IN1 (\U99/S5_q ), .OUT     (\U99/U39/2_0 ));    X_OR2 \U99/U39/U99/n57  (.IN0 (\U99/U39/2_0 ), .IN1 (\U99/S2_q ), .OUT     (\U99/n57 ));    X_OR2 \U99/U43/U99/n31/2_0  (.IN0 (\U99/n30 ), .IN1 (\U99/n29 ), .OUT     (\U99/U43/2_0 ));    X_OR2 \U99/U43/U99/n31  (.IN0 (\U99/U43/2_0 ), .IN1 (\U99/n14 ), .OUT     (\U99/n31 ));    X_AND2 \U99/U49/U99/n13/2_0  (.IN0 (n176), .IN1 (\U99/n35 ), .OUT     (\U99/U49/2_0 ));    X_AND2 \U99/U49/U99/n13  (.IN0 (\U99/U49/2_0 ), .IN1 (n177), .OUT     (\U99/n13 ));    X_OR2 \U99/U53/U99/n56/2_0  (.IN0 (\U99/S5_q ), .IN1 (\U99/S1_q ), .OUT     (\U99/U53/2_0 ));    X_OR2 \U99/U53/U99/n56  (.IN0 (\U99/U53/2_0 ), .IN1 (\U99/S2_q ), .OUT     (\U99/U53/U99/n56_2_INV ));    X_AND2 \U99/U58/U99/n42/2_0  (.IN0 (\U99/S4_q ), .IN1 (n177), .OUT     (\U99/U58/2_0 ));    X_AND2 \U99/U58/U99/n42/2_1  (.IN0 (n176), .IN1 (\U99/n41 ), .OUT     (\U99/U58/2_1 ));    X_AND2 \U99/U58/U99/n42  (.IN0 (\U99/U58/2_0 ), .IN1 (\U99/U58/2_1 ), .OUT     (\U99/n42 ));    X_AND2 \U99/U64/U99/n48/2_0  (.IN0 (\U99/S1_q ), .IN1 (n178), .OUT     (\U99/U64/2_0 ));    X_AND2 \U99/U64/U99/n48/2_1  (.IN0 (n176), .IN1 (\U99/n47 ), .OUT     (\U99/U64/2_1 ));    X_AND2 \U99/U64/U99/n48  (.IN0 (\U99/U64/2_0 ), .IN1 (\U99/U64/2_1 ), .OUT     (\U99/n48 ));    X_INV \U99/U41_2_INV_96  (.IN (\U99/U41_2_INV ), .OUT (\U99/n29 ));    X_INV \U99/U44_2_INV_97  (.IN (\U99/U44_2_INV ), .OUT (\U99/n34 ));    X_INV \U99/U45_2_INV_98  (.IN (\U99/U45_2_INV ), .OUT (\U99/n33 ));    X_INV \U99/U47_2_INV_99  (.IN (\U99/U47_2_INV ), .OUT (\U99/n14 ));    X_INV \U99/U51_2_INV_100  (.IN (\U99/U51_2_INV ), .OUT (\U99/n36 ));    X_INV \U99/U56_2_INV_101  (.IN (\U99/U56_2_INV ), .OUT (\U99/n43 ));    X_INV \U99/U60_2_INV_102  (.IN (\U99/U60_2_INV ), .OUT (\U99/n46 ));    X_INV \U99/U62_2_INV_103  (.IN (\U99/U62_2_INV ), .OUT (\U99/n49 ));    X_INV \U99/U66_2_INV_104  (.IN (\U99/U66_2_INV ), .OUT (\U99/n50 ));    X_INV \U99/U68_2_INV_105  (.IN (\U99/U68_2_INV ), .OUT (\U99/n53 ));    X_INV \U99/U53/U99/n56_2_INV_106  (.IN (\U99/U53/U99/n56_2_INV ), .OUT     (\U99/n56 ));    X_INV \U99/U36/$1I20_GTS_TRI_2_INV_107  (.IN (GTS), .OUT     (\U99/U36/$1I20_GTS_TRI_2_INV ));    X_INV \U99/U37/$1I20_GTS_TRI_2_INV_108  (.IN (GTS), .OUT     (\U99/U37/$1I20_GTS_TRI_2_INV ));    X_INV \U99/U38/$1I20_GTS_TRI_2_INV_109  (.IN (GTS), .OUT     (\U99/U38/$1I20_GTS_TRI_2_INV ));    X_ONE VCC_110 (.OUT (VCC));    X_ZERO GND_111 (.OUT (GND));    X_PD NGD2VER_PD_90 (.OUT (GSR) );    X_PD NGD2VER_PD_92 (.OUT (GTS) );  endmodule