?? time_sim.vhd
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-- Xilinx VHDL produced by program ngd2vhdl, Version M1.4.12-- Date: Tue Jan 6 16:03:32 1998-- Design file: time_sim.nga-- Device: 4005epc84-2----- CELL ROC ------- Model for Reset-On-Configuration Celllibrary IEEE;use IEEE.std_logic_1164.all;use IEEE.VITAL_Timing.all;entity ROC is generic ( InstancePath: STRING := "*"; WIDTH : Time := 0 ns) ; port( O : out std_ulogic := '1' ) ; attribute VITAL_LEVEL0 of ROC : entity is TRUE ;end ROC ;architecture ROC_V of ROC isattribute VITAL_LEVEL0 of ROC_V : architecture is TRUE ;begin ONE_SHOT: process begin if (WIDTH <= 0 ns) then assert FALSE report "*** Error: a positive value of WIDTH must be specified ***" severity failure; else wait for WIDTH; O <= '0' ; end if; wait; end process ONE_SHOT ;end ROC_V ;configuration CFG_ROC_V of ROC is for ROC_V end for ;end CFG_ROC_V ;----- CELL TOC ------- Model for Tristate-On-Configuration Celllibrary IEEE;use IEEE.std_logic_1164.all;use IEEE.VITAL_Timing.all;entity TOC is generic ( InstancePath: STRING := "*"); port( O : out std_ulogic := '0' ) ; attribute VITAL_LEVEL0 of TOC : entity is TRUE ;end TOC ;architecture TOC_V of TOC isattribute VITAL_LEVEL0 of TOC_V : architecture is TRUE ;begin ONE_SHOT: process begin wait; end process ONE_SHOT ;end TOC_V ;configuration CFG_TOC_V of TOC is for TOC_V end for ;end CFG_TOC_V ;library IEEE;use IEEE.STD_LOGIC_1164.ALL;library SIMPRIM;use SIMPRIM.VCOMPONENTS.ALL;use SIMPRIM.VPACKAGE.ALL;entity BINARY is port ( CLOCK : in STD_LOGIC := 'X' ; RESET : in STD_LOGIC := 'X' ; A : in STD_LOGIC := 'X' ; B : in STD_LOGIC := 'X' ; C : in STD_LOGIC := 'X' ; D : in STD_LOGIC := 'X' ; E : in STD_LOGIC := 'X' ; SINGLE : out STD_LOGIC ; MULTI : out STD_LOGIC ; CONTIG : out STD_LOGIC ) ;end BINARY ;architecture STRUCTURE of BINARY is component ROC port ( O : out STD_ULOGIC ) ; end component ; component TOC port ( O : out STD_ULOGIC ) ; end component ; signal N78 , N79 , N80 , N81 , N82 , N83 , N84 , N183 , N184 , N185 , N145 , N147 , N146 , N150 , N148 , N149 , N151 , N123 , N152 , N128 , N129 , N153 , N154 , N155 , N119 , N157 , N156 , N127 , N158 , N159 , N160 , N161 , N163 , N121 , N162 , N125 , N124 , N164 , N165 , N118 , N122 , N166 , N167 , N168 , N169 , N170 , N171 , N172 , N173 , N174 , N175 , N120 , N178 , N177 , N176 , N179 , N180 , N181 , N182 , U101_1I20_GTS_TRI , U102_1I20_GTS_TRI , U103_1I20_GTS_TRI , CS_REG_0_1I13_GSR_OR , CS_REG_1_1I13_GSR_OR , CS_REG_2_1I13_GSR_OR , U94_CLKIO_BUFSIG , U108_2_0 , U113_2_0 , U116_2_0 , U126_2_0 , U135_2_0 , U135_2_1 , U137_2_0 , U144_2_0 , U147_2_0 , U151_2_0 , U151_2_1 , U153_2_0 , U155_2_0 , U106_2_INV , U107_2_INV , U109_2_INV , U111_2_INV , U112_2_INV , U120_2_INV , U127_2_INV , U128_2_INV , U136_2_INV , U139_2_INV , U143_2_INV , U148_2_INV , U135_N125_2_INV , U151_N119_2_INV , U101_1I20_GTS_TRI_2_INV , U102_1I20_GTS_TRI_2_INV , U103_1I20_GTS_TRI_2_INV , GND , GSR , VCC , GTS : STD_LOGIC ; signal CS : STD_LOGIC_VECTOR ( 2 downto 0 ); begin U95 : X_BUF port map ( I => RESET , O => N79 ) ; U96 : X_BUF port map ( I => A , O => N80 ) ; U97 : X_BUF port map ( I => B , O => N81 ) ; U98 : X_BUF port map ( I => C , O => N82 ) ; U99 : X_BUF port map ( I => D , O => N83 ) ; U100 : X_BUF port map ( I => E , O => N84 ) ; U104 : X_INV port map ( I => CS(2) , O => N145 ) ; U105 : X_OR2 port map ( I0 => CS(0) , I1 => N145 , O => N147 ) ; U106 : X_AND2 port map ( I0 => CS(0) , I1 => CS(1) , O => U106_2_INV ) ; U107 : X_AND2 port map ( I0 => N146 , I1 => N147 , O => U107_2_INV ) ; U109 : X_AND2 port map ( I0 => N148 , I1 => CS(2) , O => U109_2_INV ) ; U110 : X_INV port map ( I => CS(1) , O => N148 ) ; U111 : X_AND2 port map ( I0 => N149 , I1 => N150 , O => U111_2_INV ) ; U112 : X_OR2 port map ( I0 => N123 , I1 => N83 , O => U112_2_INV ) ; U114 : X_INV port map ( I => N84 , O => N153 ) ; U115 : X_OR2 port map ( I0 => N153 , I1 => CS(0) , O => N154 ) ; U117 : X_INV port map ( I => N119 , O => N155 ) ; U118 : X_OR2 port map ( I0 => CS(0) , I1 => N155 , O => N157 ) ; U119 : X_OR2 port map ( I0 => N127 , I1 => CS(1) , O => N156 ) ; U120 : X_AND2 port map ( I0 => N156 , I1 => N157 , O => U120_2_INV ) ; U121 : X_XOR2 port map ( I0 => N82 , I1 => N81 , O => N158 ) ; U122 : X_AND2 port map ( I0 => N158 , I1 => N80 , O => N159 ) ; U123 : X_OR2 port map ( I0 => CS(2) , I1 => N159 , O => N127 ) ; U124 : X_INV port map ( I => CS(0) , O => N160 ) ; U125 : X_INV port map ( I => CS(2) , O => N161 ) ; U127 : X_AND2 port map ( I0 => N161 , I1 => N125 , O => U127_2_INV ) ; U128 : X_AND2 port map ( I0 => N162 , I1 => N163 , O => U128_2_INV ) ; U129 : X_OR2 port map ( I0 => N80 , I1 => N83 , O => N164 ) ; U130 : X_AND2 port map ( I0 => N164 , I1 => N118 , O => N165 ) ; U131 : X_OR2 port map ( I0 => N119 , I1 => N165 , O => N122 ) ; U132 : X_AND2 port map ( I0 => N84 , I1 => CS(1) , O => N121 ) ; U133 : X_INV port map ( I => N82 , O => N166 ) ; U134 : X_INV port map ( I => N80 , O => N167 ) ; U136 : X_OR2 port map ( I0 => N123 , I1 => N83 , O => U136_2_INV ) ; U138 : X_INV port map ( I => N80 , O => N170 ) ; U139 : X_AND2 port map ( I0 => CS(1) , I1 => N170 , O => U139_2_INV ) ; U140 : X_AND2 port map ( I0 => N171 , I1 => CS(0) , O => N172 ) ; U141 : X_OR2 port map ( I0 => CS(2) , I1 => N172 , O => N123 ) ; U142 : X_INV port map ( I => CS(2) , O => N173 ) ; U143 : X_OR2 port map ( I0 => N121 , I1 => N173 , O => U143_2_INV ) ; U145 : X_INV port map ( I => N177 , O => N178 ) ; U146 : X_INV port map ( I => CS(1) , O => N176 ) ; U148 : X_OR2 port map ( I0 => N178 , I1 => CS(0) , O => U148_2_INV ) ; U149 : X_INV port map ( I => N81 , O => N179 ) ; U150 : X_INV port map ( I => N80 , O => N180 ) ; U152 : X_INV port map ( I => CS(2) , O => N181 ) ; U154 : X_INV port map ( I => CS(0) , O => N182 ) ; U101_1I20 : X_BUF port map ( I => N183 , O => U101_1I20_GTS_TRI ) ; U101_1I20_GTS_TRI_0 : X_TRI port map ( I => U101_1I20_GTS_TRI , O => SINGLE , CTL => U101_1I20_GTS_TRI_2_INV ) ; U102_1I20 : X_BUF port map ( I => N184 , O => U102_1I20_GTS_TRI ) ; U102_1I20_GTS_TRI_1 : X_TRI port map ( I => U102_1I20_GTS_TRI , O => MULTI , CTL => U102_1I20_GTS_TRI_2_INV ) ; U103_1I20 : X_BUF port map ( I => N185 , O => U103_1I20_GTS_TRI ) ; U103_1I20_GTS_TRI_2 : X_TRI port map ( I => U103_1I20_GTS_TRI , O => CONTIG , CTL => U103_1I20_GTS_TRI_2_INV ) ; CS_REG_0_1I13 : X_FF port map ( I => N152 , CLK => N78 , CE => VCC , SET => CS_REG_0_1I13_GSR_OR , RST => GND , O => CS(0) ) ; CS_REG_0_1I13_GSR_OR_3 : X_OR2 port map ( I0 => N79 , I1 => GSR , O => CS_REG_0_1I13_GSR_OR ) ; CS_REG_1_1I13 : X_FF port map ( I => N169 , CLK => N78 , CE => VCC , SET => GND , RST => CS_REG_1_1I13_GSR_OR , O => CS(1) ) ; CS_REG_1_1I13_GSR_OR_4 : X_OR2 port map ( I0 => N79 , I1 => GSR , O => CS_REG_1_1I13_GSR_OR ) ; CS_REG_2_1I13 : X_FF port map ( I => N175 , CLK => N78 , CE => VCC , SET => GND , RST => CS_REG_2_1I13_GSR_OR , O => CS(2) ) ; CS_REG_2_1I13_GSR_OR_5 : X_OR2 port map ( I0 => N79 , I1 => GSR , O => CS_REG_2_1I13_GSR_OR ) ; U94_CLKBUF : X_CKBUF port map ( I => U94_CLKIO_BUFSIG , O => N78 ) ; U94_CLKIO_BUF : X_BUF port map ( I => CLOCK , O => U94_CLKIO_BUFSIG ) ; U108_N150_2_0 : X_OR2 port map ( I0 => CS(2) , I1 => CS(0) , O => U108_2_0 ) ; U108_N150 : X_OR2 port map ( I0 => U108_2_0 , I1 => N148 , O => N150 ) ; U113_N152_2_0 : X_OR2 port map ( I0 => N129 , I1 => N151 , O => U113_2_0 ) ; U113_N152 : X_OR2 port map ( I0 => U113_2_0 , I1 => N128 , O => N152 ) ; U116_N129_2_0 : X_AND2 port map ( I0 => CS(1) , I1 => N154 , O => U116_2_0 ) ; U116_N129 : X_AND2 port map ( I0 => U116_2_0 , I1 => CS(2) , O => N129 ) ; U126_N163_2_0 : X_OR2 port map ( I0 => N160 , I1 => N121 , O => U126_2_0 ) ; U126_N163 : X_OR2 port map ( I0 => U126_2_0 , I1 => N161 , O => N163 ) ; U135_N125_2_0 : X_OR2 port map ( I0 => N167 , I1 => N166 , O => U135_2_0 ) ; U135_N125_2_1 : X_OR2 port map ( I0 => CS(1) , I1 => N81 , O => U135_2_1 ) ; U135_N125 : X_OR2 port map ( I0 => U135_2_0 , I1 => U135_2_1 , O => U135_N125_2_INV ) ; U137_N169_2_0 : X_OR2 port map ( I0 => N124 , I1 => N168 , O => U137_2_0 ) ; U137_N169 : X_OR2 port map ( I0 => U137_2_0 , I1 => N183 , O => N169 ) ; U144_N175_2_0 : X_OR2 port map ( I0 => N122 , I1 => N174 , O => U144_2_0 ) ; U144_N175 : X_OR2 port map ( I0 => U144_2_0 , I1 => N120 , O => N175 ) ; U147_N177_2_0 : X_OR2 port map ( I0 => N83 , I1 => CS(2) , O => U147_2_0 ) ; U147_N177 : X_OR2 port map ( I0 => U147_2_0 , I1 => N176 , O => N177 ) ; U151_N119_2_0 : X_OR2 port map ( I0 => N180 , I1 => N179 , O => U151_2_0 ) ; U151_N119_2_1 : X_OR2 port map ( I0 => CS(1) , I1 => N82 , O => U151_2_1 ) ; U151_N119 : X_OR2 port map ( I0 => U151_2_0 , I1 => U151_2_1 , O => U151_N119_2_INV ) ; U153_N118_2_0 : X_AND2 port map ( I0 => CS(0) , I1 => N181 , O => U153_2_0 ) ; U153_N118 : X_AND2 port map ( I0 => U153_2_0 , I1 => CS(1) , O => N118 ) ; U155_N183_2_0 : X_AND2 port map ( I0 => CS(1) , I1 => N182 , O => U155_2_0 ) ; U155_N183 : X_AND2 port map ( I0 => U155_2_0 , I1 => CS(2) , O => N183 ) ; U106_2_INV_6 : X_INV port map ( I => U106_2_INV , O => N146 ) ; U107_2_INV_7 : X_INV port map ( I => U107_2_INV , O => N185 ) ; U109_2_INV_8 : X_INV port map ( I => U109_2_INV , O => N149 ) ; U111_2_INV_9 : X_INV port map ( I => U111_2_INV , O => N184 ) ; U112_2_INV_10 : X_INV port map ( I => U112_2_INV , O => N151 ) ; U120_2_INV_11 : X_INV port map ( I => U120_2_INV , O => N128 ) ; U127_2_INV_12 : X_INV port map ( I => U127_2_INV , O => N162 ) ; U128_2_INV_13 : X_INV port map ( I => U128_2_INV , O => N124 ) ; U136_2_INV_14 : X_INV port map ( I => U136_2_INV , O => N168 ) ; U139_2_INV_15 : X_INV port map ( I => U139_2_INV , O => N171 ) ; U143_2_INV_16 : X_INV port map ( I => U143_2_INV , O => N174 ) ; U148_2_INV_17 : X_INV port map ( I => U148_2_INV , O => N120 ) ; U135_N125_2_INV_18 : X_INV port map ( I => U135_N125_2_INV , O => N125 ) ; U151_N119_2_INV_19 : X_INV port map ( I => U151_N119_2_INV , O => N119 ) ; U101_1I20_GTS_TRI_2_INV_20 : X_INV port map ( I => GTS , O => U101_1I20_GTS_TRI_2_INV ) ; U102_1I20_GTS_TRI_2_INV_21 : X_INV port map ( I => GTS , O => U102_1I20_GTS_TRI_2_INV ) ; U103_1I20_GTS_TRI_2_INV_22 : X_INV port map ( I => GTS , O => U103_1I20_GTS_TRI_2_INV ) ; VCC_23 : X_ONE port map ( O => VCC ) ; GND_24 : X_ZERO port map ( O => GND ) ; ROC_NGD2VHDL : ROC port map ( O => GSR ) ; TOC_NGD2VHDL : TOC port map ( O => GTS ) ;end STRUCTURE ;?? 快捷鍵說(shuō)明
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