?? time_sim.sdf
字號:
(DELAYFILE (SDFVERSION "2.1") (DESIGN "BINARY") (DATE "Tue Jan 6 16:03:32 1998") (VENDOR "Xilinx") (PROGRAM "Xilinx VHDL SDF writer") (VERSION "M1.4.12") (DIVIDER /) (VOLTAGE 5.00:5.00:5.00) (PROCESS "best=1.0:nom=1.0:worst=1.0") (TEMPERATURE 25.00:25.00:25.00) (TIMESCALE 1ps) (CELL (CELLTYPE "X_BUF") (INSTANCE U95) (DELAY (ABSOLUTE (PORT I (0:0:0) (0:0:0)) (IOPATH I O (2050:2050:2050) (2050:2050:2050)) ) ) ) (CELL (CELLTYPE "X_BUF") (INSTANCE U96) (DELAY (ABSOLUTE (PORT I (0:0:0) (0:0:0)) (IOPATH I O (2050:2050:2050) (2050:2050:2050)) ) ) ) (CELL (CELLTYPE "X_BUF") (INSTANCE U97) (DELAY (ABSOLUTE (PORT I (0:0:0) (0:0:0)) (IOPATH I O (2050:2050:2050) (2050:2050:2050)) ) ) ) (CELL (CELLTYPE "X_BUF") (INSTANCE U98) (DELAY (ABSOLUTE (PORT I (0:0:0) (0:0:0)) (IOPATH I O (2050:2050:2050) (2050:2050:2050)) ) ) ) (CELL (CELLTYPE "X_BUF") (INSTANCE U99) (DELAY (ABSOLUTE (PORT I (0:0:0) (0:0:0)) (IOPATH I O (2050:2050:2050) (2050:2050:2050)) ) ) ) (CELL (CELLTYPE "X_BUF") (INSTANCE U100) (DELAY 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