// Xilinx Verilog produced by program ngd2ver, Version M1.4.12// Date: Tue Jan  6 19:30:57 1998// Design file: time_sim.nga// Device: 4005epc84-2`timescale 1 ns/1 ps`uselib dir=/home/zeppelin2/tech_apps/m1_4.12/verilog/data libext=.vmd  module case_ex (A, B, C, D, MUX_OUT, SEL);    input A;    input B;    input C;    input D;    output MUX_OUT;    input [1:0] SEL;    wire n53, n54, n55, n56, n57, n58, n91, n89, n90, n83, n85, n84, n86, n87,     n88, \U46/$1I20_GTS_TRI , \U51/2_0 , \U55/2_0 , U49_2_INV, U53_2_INV,     U54_2_INV, \U55/n89_2_INV , \U46/$1I20_GTS_TRI_2_INV ;    `ifdef GTS_SIGNAL      wire GTS = `GTS_SIGNAL ;    `else      wire GTS ;    `endif    initial $sdf_annotate("time_sim.sdf");    X_BUF U40 (.IN (A), .OUT (n53));    X_BUF U41 (.IN (B), .OUT (n54));    X_BUF U42 (.IN (C), .OUT (n55));    X_BUF U43 (.IN (D), .OUT (n56));    X_BUF U44 (.IN (SEL[1]), .OUT (n57));    X_BUF U45 (.IN (SEL[0]), .OUT (n58));    X_OR2 U47 (.IN0 (n89), .IN1 (n90), .OUT (n91));    X_INV U48 (.IN (n56), .OUT (n83));    X_AND2 U49 (.IN0 (n58), .IN1 (n83), .OUT (U49_2_INV));    X_OR2 U50 (.IN0 (n55), .IN1 (n58), .OUT (n84));    X_INV U52 (.IN (n58), .OUT (n86));    X_OR2 U53 (.IN0 (n86), .IN1 (n54), .OUT (U53_2_INV));    X_OR2 U54 (.IN0 (n53), .IN1 (n58), .OUT (U54_2_INV));    X_IPAD A_PAD (.PAD (A));    X_IPAD B_PAD (.PAD (B));    X_IPAD C_PAD (.PAD (C));    X_IPAD D_PAD (.PAD (D));    X_IPAD \SEL<1>_PAD  (.PAD (SEL[1]));    X_IPAD \SEL<0>_PAD  (.PAD (SEL[0]));    X_OPAD MUX_OUT_PAD (.PAD (MUX_OUT));    X_BUF \U46/$1I20  (.IN (n91), .OUT (\U46/$1I20_GTS_TRI ));    X_TRI \U46/$1I20_GTS_TRI_32  (.IN (\U46/$1I20_GTS_TRI ), .OUT (MUX_OUT),     .CTL (\U46/$1I20_GTS_TRI_2_INV ));    X_AND2 \U51/n90/2_0  (.IN0 (n85), .IN1 (n84), .OUT (\U51/2_0 ));    X_AND2 \U51/n90  (.IN0 (\U51/2_0 ), .IN1 (n57), .OUT (n90));    X_OR2 \U55/n89/2_0  (.IN0 (n57), .IN1 (n88), .OUT (\U55/2_0 ));    X_OR2 \U55/n89  (.IN0 (\U55/2_0 ), .IN1 (n87), .OUT (\U55/n89_2_INV ));    X_INV U49_2_INV_33 (.IN (U49_2_INV), .OUT (n85));    X_INV U53_2_INV_34 (.IN (U53_2_INV), .OUT (n87));    X_INV U54_2_INV_35 (.IN (U54_2_INV), .OUT (n88));    X_INV \U55/n89_2_INV_36  (.IN (\U55/n89_2_INV ), .OUT (n89));    X_INV \U46/$1I20_GTS_TRI_2_INV_37  (.IN (GTS), .OUT     (\U46/$1I20_GTS_TRI_2_INV ));    X_PD NGD2VER_PD_30 (.OUT (GTS) );  endmodule