Xilinx Mapping Report File for Design "case_ex"          Copyright (c) 1995-1997 Xilinx, Inc.  All rights reserved.Design Information------------------Command Line   : map case_ex.ngd -o map.ncd case_ex.pcf Target Device  : x4005eTarget Package : pc84Target Speed   : -2Mapper Version : xc4000e -- M1.4.12Mapped Date    : Tue Jan  6 19:30:23 1998Design Summary--------------   Number of errors:        0   Number of warnings:      1   Number of CLBs:              1 out of   196    1%      CLB Flip Flops:       0      4 input LUTs:         2      3 input LUTs:         1   Number of bonded IOBs:       7 out of    61   11%      IOB Flops:            0      IOB Latches:          0Total equivalent gate count for design: 16Additional JTAG gate count for IOBs:    336Table of Contents-----------------Section 1 - ErrorsSection 2 - WarningsSection 3 - Design AttributesSection 4 - Removed Logic SummarySection 5 - Removed LogicSection 6 - Added LogicSection 7 - Expanded LogicSection 8 - Signal Cross-ReferenceSection 9 - Symbol Cross-ReferenceSection 10 - IOB PropertiesSection 11 - RPMsSection 12 - Guide ReportSection 1 - Errors------------------Section 2 - Warnings--------------------WARNING:baste:24 - All of the external outputs in this design are using   slew-rate-limited output drivers.  The delay on speed critical outputs can be   dramatically reduced by designating them as fast outputs in the original   design.  Please see your vendor interface documentation for specific   information on how to do this within your design-entry tool.   Note: You should be careful not to designate too many outputs which switch   together as fast, because this can cause excessive ground bounce.  For more   information on this subject, please refer to the IOB switching characteristic   guidelines for the device you are using in the Programmable Logic Data Book.Section 3 - Design Attributes-----------------------------Section 4 - Removed Logic Summary---------------------------------Section 5 - Removed Logic-------------------------Section 6 - Added Logic-----------------------Section 7 - Expanded Logic--------------------------To enable this section, set the environment variable MAP_REPORT_DETAIL to TRUEand rerun MAP.Section 8 - Signal Cross-Reference----------------------------------To enable this section, set the environment variable MAP_REPORT_DETAIL to TRUEand rerun MAP.Section 9 - Symbol Cross-Reference----------------------------------To enable this section, set the environment variable MAP_REPORT_DETAIL to TRUEand rerun MAP.Section 10 - IOB Properties---------------------------"MUX_OUT" (IOB) : SLEW=SLOWSection 11 - RPMs-----------------Section 12 - Guide Report-------------------------Guide not run on this design.