?? time_sim.vhd
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-- Xilinx VHDL produced by program ngd2vhdl, Version M1.4.12-- Date: Tue Jan 6 17:23:35 1998-- Design file: time_sim.nga-- Device: 4005epc84-2----- CELL TOC ------- Model for Tristate-On-Configuration Celllibrary IEEE;use IEEE.std_logic_1164.all;use IEEE.VITAL_Timing.all;entity TOC is generic ( InstancePath: STRING := "*"); port( O : out std_ulogic := '0' ) ; attribute VITAL_LEVEL0 of TOC : entity is TRUE ;end TOC ;architecture TOC_V of TOC isattribute VITAL_LEVEL0 of TOC_V : architecture is TRUE ;begin ONE_SHOT: process begin wait; end process ONE_SHOT ;end TOC_V ;configuration CFG_TOC_V of TOC is for TOC_V end for ;end CFG_TOC_V ;library IEEE;use IEEE.STD_LOGIC_1164.ALL;library SIMPRIM;use SIMPRIM.VCOMPONENTS.ALL;use SIMPRIM.VPACKAGE.ALL;entity CASE_EX is port ( A : in STD_LOGIC := 'X' ; B : in STD_LOGIC := 'X' ; C : in STD_LOGIC := 'X' ; D : in STD_LOGIC := 'X' ; MUX_OUT : out STD_LOGIC ; SEL : in STD_LOGIC_VECTOR ( 1 downto 0 ) ) ;end CASE_EX ;architecture STRUCTURE of CASE_EX is component TOC port ( O : out STD_ULOGIC ) ; end component ; signal N23 , N24 , N25 , N26 , N27 , N28 , N61 , N59 , N60 , N53 , N55 , N54 , N56 , N57 , N58 , U46_1I20_GTS_TRI , U51_2_0 , U55_2_0 , U49_2_INV , U53_2_INV , U54_2_INV , U55_N59_2_INV , U46_1I20_GTS_TRI_2_INV , GTS : STD_LOGIC ; begin U40 : X_BUF port map ( I => SEL(1) , O => N23 ) ; U41 : X_BUF port map ( I => SEL(0) , O => N24 ) ; U42 : X_BUF port map ( I => A , O => N25 ) ; U43 : X_BUF port map ( I => B , O => N26 ) ; U44 : X_BUF port map ( I => C , O => N27 ) ; U45 : X_BUF port map ( I => D , O => N28 ) ; U47 : X_OR2 port map ( I0 => N59 , I1 => N60 , O => N61 ) ; U48 : X_INV port map ( I => N28 , O => N53 ) ; U49 : X_AND2 port map ( I0 => N24 , I1 => N53 , O => U49_2_INV ) ; U50 : X_OR2 port map ( I0 => N27 , I1 => N24 , O => N54 ) ; U52 : X_INV port map ( I => N24 , O => N56 ) ; U53 : X_OR2 port map ( I0 => N56 , I1 => N26 , O => U53_2_INV ) ; U54 : X_OR2 port map ( I0 => N25 , I1 => N24 , O => U54_2_INV ) ; U46_1I20 : X_BUF port map ( I => N61 , O => U46_1I20_GTS_TRI ) ; U46_1I20_GTS_TRI_0 : X_TRI port map ( I => U46_1I20_GTS_TRI , O => MUX_OUT , CTL => U46_1I20_GTS_TRI_2_INV ) ; U51_N60_2_0 : X_AND2 port map ( I0 => N55 , I1 => N54 , O => U51_2_0 ) ; U51_N60 : X_AND2 port map ( I0 => U51_2_0 , I1 => N23 , O => N60 ) ; U55_N59_2_0 : X_OR2 port map ( I0 => N23 , I1 => N58 , O => U55_2_0 ) ; U55_N59 : X_OR2 port map ( I0 => U55_2_0 , I1 => N57 , O => U55_N59_2_INV ) ; U49_2_INV_1 : X_INV port map ( I => U49_2_INV , O => N55 ) ; U53_2_INV_2 : X_INV port map ( I => U53_2_INV , O => N57 ) ; U54_2_INV_3 : X_INV port map ( I => U54_2_INV , O => N58 ) ; U55_N59_2_INV_4 : X_INV port map ( I => U55_N59_2_INV , O => N59 ) ; U46_1I20_GTS_TRI_2_INV_5 : X_INV port map ( I => GTS , O => U46_1I20_GTS_TRI_2_INV ) ; TOC_NGD2VHDL : TOC port map ( O => GTS ) ;end STRUCTURE ;
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