--------------------------------------------------------------------------------Xilinx TRACE, Version M1.4.12Copyright (c) 1995-1997 Xilinx, Inc.  All rights reserved.Design file:              active_low_gr.ncdPhysical constraint file: active_low_gr.pcfDevice,speed:             xc5202,-4 (1.35__5200.5_5202.13)Report level:             summary report--------------------------------------------------------------------------------WARNING:bastw:172 - No timing constraints found, doing advanced analysis with   offsets.================================================================================Timing constraint: Default period analysis for net n188 20 items analyzed, 0 timing errors detected. Minimum period is  18.736ns.--------------------------------------------------------------------------------================================================================================Timing constraint: Default OFFSET OUT AFTER analysis for clock "n188" 8 items analyzed, 0 timing errors detected. Maximum allowable offset is  17.177ns.--------------------------------------------------------------------------------================================================================================Timing constraint: Default path analysis 17 items analyzed, 0 timing errors detected. Maximum delay is  13.187ns.--------------------------------------------------------------------------------All constraints were met.Timing summary:---------------Timing errors: 0  Score: 0Constraints cover 45 paths, 0 nets, and 57 connections (90.5% coverage)Design statistics:   Minimum period:  18.736ns (Maximum frequency:  53.373MHz)   Maximum combinational path delay:  13.187ns   Maximum output required time before clock:  17.177nsAnalysis completed Wed Jan  7 11:19:36 1998--------------------------------------------------------------------------------