-- Xilinx VHDL produced by program ngd2vhdl, Version M1.4.12-- Date: Wed Jan  7 10:01:46 1998-- Design file: time_sim.nga-- Device: 5202pc84-4----- CELL ROC ------- Model for  Reset-On-Configuration Celllibrary IEEE;use IEEE.std_logic_1164.all;use IEEE.VITAL_Timing.all;entity ROC is    generic ( InstancePath: STRING := "*";              WIDTH : Time := 0 ns) ;    port( O : out std_ulogic := '1' ) ;    attribute VITAL_LEVEL0 of ROC : entity is TRUE ;end ROC ;architecture ROC_V of ROC isattribute VITAL_LEVEL0 of ROC_V : architecture is TRUE ;begin    ONE_SHOT: process    begin      if (WIDTH <= 0 ns) then         assert FALSE report         "*** Error: a positive value of WIDTH must be specified ***"         severity failure;      else         wait for WIDTH;         O <= '0' ;      end if;      wait;    end process ONE_SHOT ;end ROC_V ;configuration CFG_ROC_V of ROC is    for ROC_V    end for ;end CFG_ROC_V ;----- CELL TOC ------- Model for  Tristate-On-Configuration Celllibrary IEEE;use IEEE.std_logic_1164.all;use IEEE.VITAL_Timing.all;entity TOC is    generic ( InstancePath: STRING := "*");    port( O : out std_ulogic := '0' ) ;    attribute VITAL_LEVEL0 of TOC : entity is TRUE ;end TOC ;architecture TOC_V of TOC isattribute VITAL_LEVEL0 of TOC_V : architecture is TRUE ;begin    ONE_SHOT: process    begin      wait;    end process ONE_SHOT ;end TOC_V ;configuration CFG_TOC_V of TOC is    for TOC_V    end for ;end CFG_TOC_V ;library IEEE;use IEEE.STD_LOGIC_1164.ALL;library SIMPRIM;use SIMPRIM.VCOMPONENTS.ALL;use SIMPRIM.VPACKAGE.ALL;entity NO_GR is  port (    RESET : in STD_LOGIC := 'X' ;    CLOCK : in STD_LOGIC := 'X' ;    DNCNT : out  STD_LOGIC_VECTOR ( 3 downto 0 );    UPCNT : out  STD_LOGIC_VECTOR ( 3 downto 0 )  ) ;end NO_GR ;architecture STRUCTURE of NO_GR is  component ROC       port ( O : out STD_ULOGIC ) ;  end component ;  component TOC       port ( O : out STD_ULOGIC ) ;  end component ;  signal N217 , N216 , N215 , N214 , N213 , N212 , N211 , N210 , N189 , N188 ,   ADD_32_PLUS_PLUS_N19 , SUB_41_MINUS_MINUS_N20 , U49_1I20_GTS_TRI ,   U50_1I20_GTS_TRI , U51_1I20_GTS_TRI , U52_1I20_GTS_TRI , U53_1I20_GTS_TRI ,   U54_1I20_GTS_TRI , U55_1I20_GTS_TRI , U56_1I20_GTS_TRI ,   UP_CNT_REG_3_1I13_GR_OR , UP_CNT_REG_2_1I13_GR_OR , UP_CNT_REG_1_1I13_GR_OR ,   UP_CNT_REG_0_1I13_GR_OR , DN_CNT_REG_3_D_IN , DN_CNT_REG_3_Q_OUT ,   DN_CNT_REG_3_1I13_GR_OR , DN_CNT_REG_2_D_IN , DN_CNT_REG_2_Q_OUT ,   DN_CNT_REG_2_1I13_GR_OR , DN_CNT_REG_1_D_IN , DN_CNT_REG_1_Q_OUT ,   DN_CNT_REG_1_1I13_GR_OR , DN_CNT_REG_0_D_IN , DN_CNT_REG_0_Q_OUT ,   DN_CNT_REG_0_1I13_GR_OR , ADD_32_PLUS_PLUS_U6_S0_1_CO_3 ,   ADD_32_PLUS_PLUS_U6_S0_1_MUX_SEL_1_3 , ADD_32_PLUS_PLUS_U6_S0_1_CO_2 ,   ADD_32_PLUS_PLUS_U6_S0_1_MUX_SEL_1_2 , ADD_32_PLUS_PLUS_U6_S0_1_CO_1 ,   ADD_32_PLUS_PLUS_U6_S0_1_MUX_SEL_1_1 , ADD_32_PLUS_PLUS_U6_S0_1_CO_0 ,   ADD_32_PLUS_PLUS_U6_S0_1_MUX_SEL_1_0 , ADD_32_PLUS_PLUS_U6_GND ,   ADD_32_PLUS_PLUS_U6_S0_1_CY_MUX_1_2_AND0 ,   ADD_32_PLUS_PLUS_U6_S0_1_CY_MUX_1_2_AND1 ,   ADD_32_PLUS_PLUS_U6_S0_1_CY_MUX_1_1_AND0 ,   ADD_32_PLUS_PLUS_U6_S0_1_CY_MUX_1_1_AND1 ,   ADD_32_PLUS_PLUS_U6_S0_1_CY_MUX_1_0_AND0 ,   ADD_32_PLUS_PLUS_U6_S0_1_CY_MUX_1_0_AND1 ,   ADD_32_PLUS_PLUS_U6_S0_1_CY_MUX_0_3_AND0 ,   ADD_32_PLUS_PLUS_U6_S0_1_CY_MUX_0_3_AND1 , SUB_41_MINUS_MINUS_U6_S0_1_CO_3 ,   SUB_41_MINUS_MINUS_U6_S0_1_MUX_SEL_1_3 , SUB_41_MINUS_MINUS_U6_S0_1_CO_2 ,   SUB_41_MINUS_MINUS_U6_S0_1_MUX_SEL_1_2 , SUB_41_MINUS_MINUS_U6_S0_1_CO_1 ,   SUB_41_MINUS_MINUS_U6_S0_1_MUX_SEL_1_1 , SUB_41_MINUS_MINUS_U6_S0_1_CO_0 ,   SUB_41_MINUS_MINUS_U6_S0_1_MUX_SEL_1_0 , SUB_41_MINUS_MINUS_U6_GND ,   SUB_41_MINUS_MINUS_U6_S0_1_CY_MUX_1_2_AND0 ,   SUB_41_MINUS_MINUS_U6_S0_1_CY_MUX_1_2_AND1 ,   SUB_41_MINUS_MINUS_U6_S0_1_CY_MUX_1_1_AND0 ,   SUB_41_MINUS_MINUS_U6_S0_1_CY_MUX_1_1_AND1 ,   SUB_41_MINUS_MINUS_U6_S0_1_CY_MUX_1_0_AND0 ,   SUB_41_MINUS_MINUS_U6_S0_1_CY_MUX_1_0_AND1 ,   SUB_41_MINUS_MINUS_U6_S0_1_CY_MUX_0_3_AND0 ,   SUB_41_MINUS_MINUS_U6_S0_1_CY_MUX_0_3_AND1 , U58_CLKIO_BUFSIG ,   ADD_32_PLUS_PLUS_U6_S0_1_XOR7_MUX_SEL_1_3_1_INV ,   ADD_32_PLUS_PLUS_U6_S0_1_XOR5_MUX_SEL_1_2_1_INV ,   ADD_32_PLUS_PLUS_U6_S0_1_XOR3_MUX_SEL_1_1_1_INV ,   ADD_32_PLUS_PLUS_U6_S0_1_XOR1_MUX_SEL_1_0_1_INV ,   ADD_32_PLUS_PLUS_U6_S0_1_CY_MUX_1_2_AND0_1_INV ,   ADD_32_PLUS_PLUS_U6_S0_1_CY_MUX_1_1_AND0_1_INV ,   ADD_32_PLUS_PLUS_U6_S0_1_CY_MUX_1_0_AND0_1_INV ,   ADD_32_PLUS_PLUS_U6_S0_1_CY_MUX_0_3_AND0_1_INV ,   SUB_41_MINUS_MINUS_U6_S0_1_XOR7_MUX_SEL_1_3_1_INV ,   SUB_41_MINUS_MINUS_U6_S0_1_XOR5_MUX_SEL_1_2_1_INV ,   SUB_41_MINUS_MINUS_U6_S0_1_XOR3_MUX_SEL_1_1_1_INV ,   SUB_41_MINUS_MINUS_U6_S0_1_XOR1_MUX_SEL_1_0_1_INV ,   SUB_41_MINUS_MINUS_U6_S0_1_CY_MUX_1_2_AND0_1_INV ,   SUB_41_MINUS_MINUS_U6_S0_1_CY_MUX_1_1_AND0_1_INV ,   SUB_41_MINUS_MINUS_U6_S0_1_CY_MUX_1_0_AND0_1_INV ,   SUB_41_MINUS_MINUS_U6_S0_1_CY_MUX_0_3_AND0_1_INV , U49_1I20_GTS_TRI_2_INV ,   U50_1I20_GTS_TRI_2_INV , U51_1I20_GTS_TRI_2_INV , U52_1I20_GTS_TRI_2_INV ,   U53_1I20_GTS_TRI_2_INV , U54_1I20_GTS_TRI_2_INV , U55_1I20_GTS_TRI_2_INV ,   U56_1I20_GTS_TRI_2_INV , GND , GR , VCC , GTS : STD_LOGIC ;  signal ARG58 : STD_LOGIC_VECTOR ( 3 downto 0 );  signal ARG139 : STD_LOGIC_VECTOR ( 3 downto 0 );  begin    U57 : X_BUF       port map ( I => RESET , O => N189 ) ;    ADD_32_PLUS_PLUS_N19_ONE : X_ONE       port map ( O => ADD_32_PLUS_PLUS_N19 ) ;    SUB_41_MINUS_MINUS_N20_ZERO : X_ZERO       port map ( O => SUB_41_MINUS_MINUS_N20 ) ;    U49_1I20 : X_BUF       port map ( I => N217 , O => U49_1I20_GTS_TRI ) ;    U49_1I20_GTS_TRI_0 : X_TRI       port map ( I => U49_1I20_GTS_TRI , O => DNCNT(0) ,       CTL => U49_1I20_GTS_TRI_2_INV ) ;    U50_1I20 : X_BUF       port map ( I => N216 , O => U50_1I20_GTS_TRI ) ;    U50_1I20_GTS_TRI_1 : X_TRI       port map ( I => U50_1I20_GTS_TRI , O => DNCNT(1) ,       CTL => U50_1I20_GTS_TRI_2_INV ) ;    U51_1I20 : X_BUF       port map ( I => N215 , O => U51_1I20_GTS_TRI ) ;    U51_1I20_GTS_TRI_2 : X_TRI       port map ( I => U51_1I20_GTS_TRI , O => DNCNT(2) ,       CTL => U51_1I20_GTS_TRI_2_INV ) ;    U52_1I20 : X_BUF       port map ( I => N214 , O => U52_1I20_GTS_TRI ) ;    U52_1I20_GTS_TRI_3 : X_TRI       port map ( I => U52_1I20_GTS_TRI , O => DNCNT(3) ,       CTL => U52_1I20_GTS_TRI_2_INV ) ;    U53_1I20 : X_BUF       port map ( I => N213 , O => U53_1I20_GTS_TRI ) ;    U53_1I20_GTS_TRI_4 : X_TRI       port map ( I => U53_1I20_GTS_TRI , O => UPCNT(0) ,       CTL => U53_1I20_GTS_TRI_2_INV ) ;    U54_1I20 : X_BUF       port map ( I => N212 , O => U54_1I20_GTS_TRI ) ;    U54_1I20_GTS_TRI_5 : X_TRI       port map ( I => U54_1I20_GTS_TRI , O => UPCNT(1) ,       CTL => U54_1I20_GTS_TRI_2_INV ) ;    U55_1I20 : X_BUF       port map ( I => N211 , O => U55_1I20_GTS_TRI ) ;    U55_1I20_GTS_TRI_6 : X_TRI       port map ( I => U55_1I20_GTS_TRI , O => UPCNT(2) ,       CTL => U55_1I20_GTS_TRI_2_INV ) ;    U56_1I20 : X_BUF       port map ( I => N210 , O => U56_1I20_GTS_TRI ) ;    U56_1I20_GTS_TRI_7 : X_TRI       port map ( I => U56_1I20_GTS_TRI , O => UPCNT(3) ,       CTL => U56_1I20_GTS_TRI_2_INV ) ;    UP_CNT_REG_3_1I13 : X_FF       port map ( I => ARG58(3) , CLK => N188 , CE => VCC , SET => GND ,       RST => UP_CNT_REG_3_1I13_GR_OR , O => N210 ) ;    UP_CNT_REG_3_1I13_GR_OR_8 : X_OR2       port map ( I0 => N189 , I1 => GR , O => UP_CNT_REG_3_1I13_GR_OR ) ;    UP_CNT_REG_2_1I13 : X_FF       port map ( I => ARG58(2) , CLK => N188 , CE => VCC , SET => GND ,       RST => UP_CNT_REG_2_1I13_GR_OR , O => N211 ) ;    UP_CNT_REG_2_1I13_GR_OR_9 : X_OR2       port map ( I0 => N189 , I1 => GR , O => UP_CNT_REG_2_1I13_GR_OR ) ;    UP_CNT_REG_1_1I13 : X_FF       port map ( I => ARG58(1) , CLK => N188 , CE => VCC , SET => GND ,       RST => UP_CNT_REG_1_1I13_GR_OR , O => N212 ) ;    UP_CNT_REG_1_1I13_GR_OR_10 : X_OR2       port map ( I0 => N189 , I1 => GR , O => UP_CNT_REG_1_1I13_GR_OR ) ;    UP_CNT_REG_0_1I13 : X_FF       port map ( I => ARG58(0) , CLK => N188 , CE => VCC , SET => GND ,       RST => UP_CNT_REG_0_1I13_GR_OR , O => N213 ) ;    UP_CNT_REG_0_1I13_GR_OR_11 : X_OR2       port map ( I0 => N189 , I1 => GR , O => UP_CNT_REG_0_1I13_GR_OR ) ;    DN_CNT_REG_3_SYM1 : X_INV       port map ( I => ARG139(3) , O => DN_CNT_REG_3_D_IN ) ;    DN_CNT_REG_3_SYM2 : X_INV       port map ( I => DN_CNT_REG_3_Q_OUT , O => N214 ) ;    DN_CNT_REG_3_1I13 : X_FF       port map ( I => DN_CNT_REG_3_D_IN , CLK => N188 , CE => VCC , SET => GND       , RST => DN_CNT_REG_3_1I13_GR_OR , O => DN_CNT_REG_3_Q_OUT ) ;    DN_CNT_REG_3_1I13_GR_OR_12 : X_OR2       port map ( I0 => N189 , I1 => GR , O => DN_CNT_REG_3_1I13_GR_OR ) ;    DN_CNT_REG_2_SYM1 : X_INV       port map ( I => ARG139(2) , O => DN_CNT_REG_2_D_IN ) ;    DN_CNT_REG_2_SYM2 : X_INV       port map ( I => DN_CNT_REG_2_Q_OUT , O => N215 ) ;    DN_CNT_REG_2_1I13 : X_FF       port map ( I => DN_CNT_REG_2_D_IN , CLK => N188 , CE => VCC , SET => GND       , RST => DN_CNT_REG_2_1I13_GR_OR , O => DN_CNT_REG_2_Q_OUT ) ;    DN_CNT_REG_2_1I13_GR_OR_13 : X_OR2       port map ( I0 => N189 , I1 => GR , O => DN_CNT_REG_2_1I13_GR_OR ) ;    DN_CNT_REG_1_SYM1 : X_INV       port map ( I => ARG139(1) , O => DN_CNT_REG_1_D_IN ) ;    DN_CNT_REG_1_SYM2 : X_INV       port map ( I => DN_CNT_REG_1_Q_OUT , O => N216 ) ;    DN_CNT_REG_1_1I13 : X_FF       port map ( I => DN_CNT_REG_1_D_IN , CLK => N188 , CE => VCC , SET => GND       , RST => DN_CNT_REG_1_1I13_GR_OR , O => DN_CNT_REG_1_Q_OUT ) ;    DN_CNT_REG_1_1I13_GR_OR_14 : X_OR2       port map ( I0 => N189 , I1 => GR , O => DN_CNT_REG_1_1I13_GR_OR ) ;    DN_CNT_REG_0_SYM1 : X_INV       port map ( I => ARG139(0) , O => DN_CNT_REG_0_D_IN ) ;    DN_CNT_REG_0_SYM2 : X_INV       port map ( I => DN_CNT_REG_0_Q_OUT , O => N217 ) ;    DN_CNT_REG_0_1I13 : X_FF