// VERILOG TestFixture Template produced by ngd2ver M1.4.12// Design file: time_sim.nga// Date:Tue Jan  6 18:27:20 1998// ATTENTION: This file was created by NGD2VER and may therefore be overwritten// by subsequent runs of NGD2VER. Xilinx recommends that you copy this file to// a new name, or 'paste' this text into another file, to avoid accidental loss// of data.`timescale 1 ns/1 psmodule test;  reg A;  reg B;  reg C;  reg D;  reg E;  wire SIG;  reg [4:0] SEL;  reg GTS;  `define GTS_SIGNAL test.GTS  mux_tbuf uut ( .A (A) , .B (B) , .C (C) , .D (D) , .E (E) , .SIG (SIG) , .SEL (SEL) );  initial begin    $timeformat(-9,3,"ns",12);    $shm_open("time_sim.shm");    $shm_probe("AS");  end  initial begin    $display("           T ABCDESS ");    $display("           i      IE ");    $display("           m      GL ");    $display("           e       [ ");    $display("                   4 ");    $display("                   : ");    $display("                   0 ");    $display("                   ] ");    $monitor("%t",$realtime,, A, B, C, D, E, SIG, "%h", SEL );  end  initial begin      `GTS_SIGNAL = 0;    #100      A = 0 ;      B = 0 ;      C = 0 ;      D = 0 ;      E = 0 ;      SEL = 0 ;    #1000 $stop;    // #1000 $finish;  endendmodule