--------------------------------------------------------------------------------Xilinx TRACE, Version M1.4.12Copyright (c) 1995-1997 Xilinx, Inc.  All rights reserved.Design file:              mux_gate16.ncdPhysical constraint file: mux_gate16.pcfDevice,speed:             xc4005e,-2 (x1_0.86  PRELIMINARY)Report level:             summary report--------------------------------------------------------------------------------WARNING:bastw:172 - No timing constraints found, doing advanced analysis with   offsets.================================================================================Timing constraint: Default path analysis 32 items analyzed, 0 timing errors detected. Maximum delay is  21.704ns.--------------------------------------------------------------------------------All constraints were met.Timing summary:---------------Timing errors: 0  Score: 0Constraints cover 32 paths, 0 nets, and 44 connections (100.0% coverage)Design statistics:   Maximum combinational path delay:  21.704nsAnalysis completed Tue Jan  6 16:26:20 1998--------------------------------------------------------------------------------