-- Xilinx VHDL produced by program ngd2vhdl, Version M1.4.12-- Date: Tue Jan  6 16:23:33 1998-- Design file: time_sim.nga-- Device: 4005epc84-2----- CELL TOC ------- Model for  Tristate-On-Configuration Celllibrary IEEE;use IEEE.std_logic_1164.all;use IEEE.VITAL_Timing.all;entity TOC is    generic ( InstancePath: STRING := "*");    port( O : out std_ulogic := '0' ) ;    attribute VITAL_LEVEL0 of TOC : entity is TRUE ;end TOC ;architecture TOC_V of TOC isattribute VITAL_LEVEL0 of TOC_V : architecture is TRUE ;begin    ONE_SHOT: process    begin      wait;    end process ONE_SHOT ;end TOC_V ;configuration CFG_TOC_V of TOC is    for TOC_V    end for ;end CFG_TOC_V ;library IEEE;use IEEE.STD_LOGIC_1164.ALL;library SIMPRIM;use SIMPRIM.VCOMPONENTS.ALL;use SIMPRIM.VPACKAGE.ALL;entity MUX_TBUF is  port (    A : in STD_LOGIC := 'X' ;    B : in STD_LOGIC := 'X' ;    C : in STD_LOGIC := 'X' ;    D : in STD_LOGIC := 'X' ;    E : in STD_LOGIC := 'X' ;    SIG : out STD_LOGIC ;    SEL : in  STD_LOGIC_VECTOR ( 4 downto 0 )  ) ;end MUX_TBUF ;architecture STRUCTURE of MUX_TBUF is  component TOC       port ( O : out STD_ULOGIC ) ;  end component ;  signal N227 , N191 , SIG_TRI_ENABLE151 , N188 , SIG_TRI_ENABLE55 , N189 ,   SIG_TRI_ENABLE87 , N187 , SIG_TRI_ENABLE , N190 , SIG_TRI_ENABLE119 ,   U105_1I20_GTS_TRI , SIG_TRI5_2_INV , SIG_TRI2_2_INV , SIG_TRI3_2_INV ,   SIG_TRI_2_INV , SIG_TRI4_2_INV , U105_1I20_GTS_TRI_2_INV , GTS : STD_LOGIC ;  begin    SIG_TRI5 : X_TRI       port map ( I => N191 , O => N227 , CTL => SIG_TRI5_2_INV ) ;    SIG_TRI2 : X_TRI       port map ( I => N188 , O => N227 , CTL => SIG_TRI2_2_INV ) ;    SIG_TRI3 : X_TRI       port map ( I => N189 , O => N227 , CTL => SIG_TRI3_2_INV ) ;    SIG_TRI : X_TRI       port map ( I => N187 , O => N227 , CTL => SIG_TRI_2_INV ) ;    SIG_TRI4 : X_TRI       port map ( I => N190 , O => N227 , CTL => SIG_TRI4_2_INV ) ;    U95 : X_BUF       port map ( I => SEL(4) , O => SIG_TRI_ENABLE151 ) ;    U96 : X_BUF       port map ( I => SEL(3) , O => SIG_TRI_ENABLE119 ) ;    U97 : X_BUF       port map ( I => SEL(2) , O => SIG_TRI_ENABLE87 ) ;    U98 : X_BUF       port map ( I => SEL(1) , O => SIG_TRI_ENABLE55 ) ;    U99 : X_BUF       port map ( I => SEL(0) , O => SIG_TRI_ENABLE ) ;    U100 : X_BUF       port map ( I => A , O => N187 ) ;    U101 : X_BUF       port map ( I => B , O => N188 ) ;    U102 : X_BUF       port map ( I => C , O => N189 ) ;    U103 : X_BUF       port map ( I => D , O => N190 ) ;    U104 : X_BUF       port map ( I => E , O => N191 ) ;    U105_1I20 : X_BUF       port map ( I => N227 , O => U105_1I20_GTS_TRI ) ;    U105_1I20_GTS_TRI_0 : X_TRI       port map ( I => U105_1I20_GTS_TRI , O => SIG ,       CTL => U105_1I20_GTS_TRI_2_INV ) ;    SIG_TRI5_2_INV_1 : X_INV       port map ( I => SIG_TRI_ENABLE151 , O => SIG_TRI5_2_INV ) ;    SIG_TRI2_2_INV_2 : X_INV       port map ( I => SIG_TRI_ENABLE55 , O => SIG_TRI2_2_INV ) ;    SIG_TRI3_2_INV_3 : X_INV       port map ( I => SIG_TRI_ENABLE87 , O => SIG_TRI3_2_INV ) ;    SIG_TRI_2_INV_4 : X_INV       port map ( I => SIG_TRI_ENABLE , O => SIG_TRI_2_INV ) ;    SIG_TRI4_2_INV_5 : X_INV       port map ( I => SIG_TRI_ENABLE119 , O => SIG_TRI4_2_INV ) ;    U105_1I20_GTS_TRI_2_INV_6 : X_INV       port map ( I => GTS , O => U105_1I20_GTS_TRI_2_INV ) ;    TOC_NGD2VHDL : TOC       port map ( O => GTS ) ;end STRUCTURE ;