## Copyright (c) 2004 Xilinx, Inc. All Rights Reserved.
## You may copy and modify these files for your own internal use solely with
## Xilinx programmable logic devices and  Xilinx EDK system or create IP
## modules solely for Xilinx programmable logic devices and Xilinx EDK system.
## No rights are granted to distribute any files unless they are distributed in
## Xilinx programmable logic devices.
###################################################################
##
## Name     : opb_mdm
## Desc     : Microprocessor Peripheral Description
##          : Automatically generated by PsfUtility
##
###################################################################

BEGIN opb_mdm

## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION HDL = VHDL
OPTION IMP_NETLIST = TRUE
OPTION STYLE = HDL
OPTION CORE_STATE = ACTIVE
OPTION IP_GROUP = LOGICORE
OPTION ARCH_SUPPORT = virtex4


## Bus Interfaces
BUS_INTERFACE BUS = SOPB, BUS_STD = OPB, BUS_TYPE = SLAVE
BUS_INTERFACE BUS = SFSL0, BUS_STD = FSL, BUS_TYPE = SLAVE
BUS_INTERFACE BUS = MFSL0, BUS_STD = FSL, BUS_TYPE = MASTER

## Generics for VHDL or Parameters for Verilog
PARAMETER C_BASEADDR = 0xffffffff, DT = STD_LOGIC_VECTOR, BUS = SOPB, MIN_SIZE = 0x100
PARAMETER C_HIGHADDR = 0x00000000, DT = STD_LOGIC_VECTOR, BUS = SOPB
PARAMETER C_OPB_DWIDTH = 32, DT = INTEGER
PARAMETER C_OPB_AWIDTH = 32, DT = INTEGER
PARAMETER C_FAMILY = virtex2, DT = STRING
PARAMETER C_MB_DBG_PORTS = 1, DT = INTEGER
PARAMETER C_USE_UART = 1, DT = INTEGER
PARAMETER C_UART_WIDTH = 32, DT = INTEGER
PARAMETER C_WRITE_FSL_PORTS = 0, DT = INTEGER

## Ports
PORT OPB_Clk = "", DIR = IN, BUS = SOPB, SIGIS = CLK
PORT OPB_Rst = OPB_Rst, DIR = IN, BUS = SOPB
PORT Interrupt = "", DIR = OUT, EDGE = RISING
PORT Debug_SYS_Rst = Debug_SYS_Rst, DIR = OUT, BUS = SOPB
PORT Debug_Rst = Debug_Rst, DIR = OUT
PORT Ext_BRK = Ext_BRK, DIR = OUT
PORT Ext_NM_BRK = Ext_NM_BRK, DIR = OUT
PORT OPB_ABus = OPB_ABus, DIR = IN, VEC = [0:C_OPB_AWIDTH-1], BUS = SOPB
PORT OPB_BE = OPB_BE, DIR = IN, VEC = [0:C_OPB_DWIDTH/8-1], BUS = SOPB
PORT OPB_RNW = OPB_RNW, DIR = IN, BUS = SOPB
PORT OPB_select = OPB_select, DIR = IN, BUS = SOPB
PORT OPB_seqAddr = OPB_seqAddr, DIR = IN, BUS = SOPB
PORT OPB_DBus = OPB_DBus, DIR = IN, VEC = [0:C_OPB_DWIDTH-1], BUS = SOPB
PORT MDM_DBus = Sl_DBus, DIR = OUT, VEC = [0:C_OPB_DWIDTH-1], BUS = SOPB
PORT MDM_errAck = Sl_errAck, DIR = OUT, BUS = SOPB
PORT MDM_retry = Sl_retry, DIR = OUT, BUS = SOPB
PORT MDM_toutSup = Sl_toutSup, DIR = OUT, BUS = SOPB
PORT MDM_xferAck = Sl_xferAck, DIR = OUT, BUS = SOPB
PORT Dbg_Clk_0 = Dbg_Clk, DIR = OUT
PORT Dbg_TDI_0 = Dbg_TDI, DIR = OUT
PORT Dbg_TDO_0 = Dbg_TDO, DIR = IN
PORT Dbg_Reg_En_0 = Dbg_Reg_En, DIR = OUT, VEC = [0:4]
PORT Dbg_Capture_0 = Dbg_Capture, DIR = OUT
PORT Dbg_Update_0 = Dbg_Update, DIR = OUT
PORT Dbg_Clk_1 = "", DIR = OUT
PORT Dbg_TDI_1 = "", DIR = OUT
PORT Dbg_TDO_1 = "", DIR = IN
PORT Dbg_Reg_En_1 = "", DIR = OUT, VEC = [0:4]
PORT Dbg_Capture_1 = "", DIR = OUT
PORT Dbg_Update_1 = "", DIR = OUT
PORT Dbg_Clk_2 = "", DIR = OUT
PORT Dbg_TDI_2 = "", DIR = OUT
PORT Dbg_TDO_2 = "", DIR = IN
PORT Dbg_Reg_En_2 = "", DIR = OUT, VEC = [0:4]
PORT Dbg_Capture_2 = "", DIR = OUT
PORT Dbg_Update_2 = "", DIR = OUT
PORT Dbg_Clk_3 = "", DIR = OUT
PORT Dbg_TDI_3 = "", DIR = OUT
PORT Dbg_TDO_3 = "", DIR = IN
PORT Dbg_Reg_En_3 = "", DIR = OUT, VEC = [0:4]
PORT Dbg_Capture_3 = "", DIR = OUT
PORT Dbg_Update_3 = "", DIR = OUT
PORT Dbg_Clk_4 = "", DIR = OUT
PORT Dbg_TDI_4 = "", DIR = OUT
PORT Dbg_TDO_4 = "", DIR = IN
PORT Dbg_Reg_En_4 = "", DIR = OUT, VEC = [0:4]
PORT Dbg_Capture_4 = "", DIR = OUT
PORT Dbg_Update_4 = "", DIR = OUT
PORT Dbg_Clk_5 = "", DIR = OUT
PORT Dbg_TDI_5 = "", DIR = OUT
PORT Dbg_TDO_5 = "", DIR = IN
PORT Dbg_Reg_En_5 = "", DIR = OUT, VEC = [0:4]
PORT Dbg_Capture_5 = "", DIR = OUT
PORT Dbg_Update_5 = "", DIR = OUT
PORT Dbg_Clk_6 = "", DIR = OUT
PORT Dbg_TDI_6 = "", DIR = OUT
PORT Dbg_TDO_6 = "", DIR = IN
PORT Dbg_Reg_En_6 = "", DIR = OUT, VEC = [0:4]
PORT Dbg_Capture_6 = "", DIR = OUT
PORT Dbg_Update_6 = "", DIR = OUT
PORT Dbg_Clk_7 = "", DIR = OUT
PORT Dbg_TDI_7 = "", DIR = OUT
PORT Dbg_TDO_7 = "", DIR = IN
PORT Dbg_Reg_En_7 = "", DIR = OUT, VEC = [0:4]
PORT Dbg_Capture_7 = "", DIR = OUT
PORT Dbg_Update_7 = "", DIR = OUT
PORT bscan_tdi = bscan_tdi, DIR = OUT
PORT bscan_reset = bscan_reset, DIR = OUT
PORT bscan_shift = bscan_shift, DIR = OUT
PORT bscan_update = bscan_update, DIR = OUT
PORT bscan_capture = bscan_capture, DIR = OUT
PORT bscan_sel1 = bscan_sel1, DIR = OUT
PORT bscan_drck1 = bscan_drck1, DIR = OUT
PORT bscan_tdo1 = bscan_tdo1, DIR = IN
PORT FSL0_S_CLK = FSL_S_Clk, DIR = out, SIGIS = CLK, BUS = SFSL0
PORT FSL0_S_READ = FSL_S_Read, DIR = out, BUS = SFSL0
PORT FSL0_S_DATA = FSL_S_Data, DIR = in, VEC = [0:31], BUS = SFSL0
PORT FSL0_S_CONTROL = FSL_S_Control, DIR = in, BUS = SFSL0
PORT FSL0_S_EXISTS = FSL_S_Exists, DIR = in, BUS = SFSL0
PORT FSL0_M_CLK = FSL_M_Clk, DIR = out, SIGIS = CLK, BUS = MFSL0
PORT FSL0_M_WRITE = FSL_M_Write, DIR = out, BUS = MFSL0
PORT FSL0_M_DATA = FSL_M_Data, DIR = out, VEC = [0:31], BUS = MFSL0
PORT FSL0_M_CONTROL = FSL_M_Control, DIR = out, BUS = MFSL0
PORT FSL0_M_FULL = FSL_M_Full, DIR = in, BUS = MFSL0

END