Classic Timing Analyzer report for division
Wed Jun 25 20:21:15 2008
Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'clk'
  6. tco
  7. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                 ;
+------------------------------+-------+---------------+----------------------------------+-------------+----------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                      ; From        ; To       ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+-------------+----------+------------+----------+--------------+
; Worst-case tco               ; N/A   ; None          ; 5.696 ns                         ; outclk~reg0 ; outclk   ; clk        ; --       ; 0            ;
; Clock Setup: 'clk'           ; N/A   ; None          ; 364.96 MHz ( period = 2.740 ns ) ; count[0]    ; count[5] ; clk        ; clk      ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;             ;          ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+-------------+----------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C3T100C6        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                          ;
+-------+------------------------------------------------+----------+-------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From     ; To          ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+----------+-------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 364.96 MHz ( period = 2.740 ns )               ; count[0] ; count[5]    ; clk        ; clk      ; None                        ; None                      ; 2.538 ns                ;
; N/A   ; 367.24 MHz ( period = 2.723 ns )               ; count[1] ; count[5]    ; clk        ; clk      ; None                        ; None                      ; 2.521 ns                ;
; N/A   ; 373.69 MHz ( period = 2.676 ns )               ; count[2] ; count[5]    ; clk        ; clk      ; None                        ; None                      ; 2.474 ns                ;
; N/A   ; 374.53 MHz ( period = 2.670 ns )               ; count[7] ; count[0]    ; clk        ; clk      ; None                        ; None                      ; 2.468 ns                ;
; N/A   ; 374.67 MHz ( period = 2.669 ns )               ; count[7] ; count[7]    ; clk        ; clk      ; None                        ; None                      ; 2.467 ns                ;
; N/A   ; 384.17 MHz ( period = 2.603 ns )               ; count[3] ; count[5]    ; clk        ; clk      ; None                        ; None                      ; 2.401 ns                ;
; N/A   ; 384.47 MHz ( period = 2.601 ns )               ; count[4] ; count[5]    ; clk        ; clk      ; None                        ; None                      ; 2.399 ns                ;
; N/A   ; 385.21 MHz ( period = 2.596 ns )               ; count[0] ; count[6]    ; clk        ; clk      ; None                        ; None                      ; 2.394 ns                ;
; N/A   ; 387.75 MHz ( period = 2.579 ns )               ; count[1] ; count[6]    ; clk        ; clk      ; None                        ; None                      ; 2.377 ns                ;
; N/A   ; 392.62 MHz ( period = 2.547 ns )               ; count[0] ; count[3]    ; clk        ; clk      ; None                        ; None                      ; 2.345 ns                ;
; N/A   ; 394.94 MHz ( period = 2.532 ns )               ; count[2] ; count[6]    ; clk        ; clk      ; None                        ; None                      ; 2.330 ns                ;
; N/A   ; 395.88 MHz ( period = 2.526 ns )               ; count[1] ; count[3]    ; clk        ; clk      ; None                        ; None                      ; 2.324 ns                ;
; N/A   ; 398.25 MHz ( period = 2.511 ns )               ; count[0] ; count[2]    ; clk        ; clk      ; None                        ; None                      ; 2.309 ns                ;
; N/A   ; 401.61 MHz ( period = 2.490 ns )               ; count[1] ; count[2]    ; clk        ; clk      ; None                        ; None                      ; 2.288 ns                ;
; N/A   ; 403.71 MHz ( period = 2.477 ns )               ; count[2] ; count[3]    ; clk        ; clk      ; None                        ; None                      ; 2.275 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[0] ; count[4]    ; clk        ; clk      ; None                        ; None                      ; 2.261 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[3] ; count[6]    ; clk        ; clk      ; None                        ; None                      ; 2.257 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[4] ; count[6]    ; clk        ; clk      ; None                        ; None                      ; 2.255 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[5] ; count[6]    ; clk        ; clk      ; None                        ; None                      ; 2.244 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[1] ; count[4]    ; clk        ; clk      ; None                        ; None                      ; 2.240 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[2] ; count[4]    ; clk        ; clk      ; None                        ; None                      ; 2.191 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[3] ; count[4]    ; clk        ; clk      ; None                        ; None                      ; 2.116 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[1] ; count[0]    ; clk        ; clk      ; None                        ; None                      ; 2.105 ns                ;