?? 10分鐘學會pld設計—2 編譯和布線.htm
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has user pin or logic cell assignments, but never been compiled before.
For best fitting results, let the compiler choose the first set of
assignments instead”，這是因為在管腳指定之前沒有compile，你只要再點save &
compile就可以了</SPAN></P>
<P align=left><SPAN class=font10 lang=EN-US
mso-bidi-font-size:12.0pt;font-family:宋體;color:black?><BR><IMG
height=118 src="10分鐘學會PLD設計—2 編譯和布線.files/image056.jpg" width=553
border=0 v:shapes="_x0000_i1060"> <O:P></O:P></SPAN></P>
<P align=left><SPAN class=font10 lang=EN-US mso-bidi-font-family:Arial?
mso-bidi-font-size:9.0pt;font-family:宋體;>MAX+PLUS II </SPAN><SPAN
class=font10
mso-bidi-font-size:9.0pt;font-family:宋體?>編譯器將檢查項目是否有錯，并對項目進行邏輯綜合，然后對設計進行布局布線，放到一個</SPAN><SPAN
class=font10 lang=EN-US mso-bidi-font-family:Arial?
mso-bidi-font-size:9.0pt;font-family:宋體;>Altera </SPAN><SPAN
class=font10
mso-bidi-font-size:9.0pt;font-family:宋體?>器件中，同時將產生報告文件、編程文件和用于時間仿真用的輸出文件</SPAN><SPAN
class=font10 lang=EN-US mso-bidi-font-size:12.0pt;font-family:宋體;
display:none;mso-hide:all;mso-font-kerning:0pt?><O:P></O:P></SPAN></P>
<P align=left><SPAN class=font10 lang=EN-US mso-bidi-font-size:
12.0pt;font-family:宋體?><O:P><SPAN class=font10
mso-bidi-font-size:9.0pt;font-family:宋體?>邏輯綜合：就是把HDL語言或原理圖翻譯成最基本的與或非門的連接關系</SPAN></O:P></SPAN></P>
<P align=left><SPAN class=font10 lang=EN-US mso-bidi-font-size:
12.0pt;font-family:宋體?><O:P><SPAN class=font10
mso-bidi-font-size:9.0pt;font-family:宋體?>布局布線：把這種<SPAN class=font10
lang=EN-US mso-bidi-font-size: 12.0pt;font-family:宋體?><SPAN class=font10
mso-bidi-font-size:9.0pt;font-family:宋體?>與或非門的</SPAN></SPAN>連接關系用芯片的內部的<SPAN
class=font10 lang=EN-US mso-bidi-font-size: 12.0pt;font-family:宋體?><SPAN
class=font10
mso-bidi-font-size:9.0pt;font-family:宋體?>可編程</SPAN></SPAN>結構和連線來實現</SPAN></O:P></SPAN></P>
<P align=left><SPAN class=font10 lang=EN-US mso-bidi-font-size:
12.0pt;font-family:宋體?><O:P></O:P></SPAN></P>
<P align=left><SPAN class=font10 font-family:宋體;color:black?
mso-bidi-font-size:12.0pt;>如果設計正確，將下圖所示，點確認<SPAN lang=EN-US><BR><IMG
height=238 src="10分鐘學會PLD設計—2 編譯和布線.files/image058.jpg" width=553
border=0 v:shapes="_x0000_i1061"> <O:P></O:P></SPAN></SPAN></P>
<P align=left><SPAN class=font10 font-family:宋體;color:black?
mso-bidi-font-size:12.0pt;>編譯后可以看到<SPAN
lang=EN-US>IO在芯片上的分布：MAX+plusII-> Froorplan
Editor<O:P></O:P></SPAN></SPAN></P>
<P align=left><SPAN class=font10 lang=EN-US
12.0pt;font-family:宋體;color:black? mso-bidi-font-size:><IMG height=314
src="10分鐘學會PLD設計—2 編譯和布線.files/image059.jpg" width=248 border=0
v:shapes="_x0000_i1062"> <O:P></O:P></SPAN></P>
<P align=left><SPAN class=font10 lang=EN-US
mso-ansi-language:EN-US;mso-fareast-language:ZH-CN;mso-bidi-language:AR-SA?
Roman?;color:black;mso-font-kerning:1.0pt; New
宋體;mso-bidi-font-family:?Times
mso-bidi-font-size:12.0pt;font-family:><BR
style="PAGE-BREAK-BEFORE: always" clear=all></SPAN></P>
<P align=left><SPAN class=font10 font-family:宋體;color:black?
mso-bidi-font-size:12.0pt;>將彈出一窗口如下圖<SPAN
lang=EN-US><O:P></O:P></SPAN></SPAN></P>
<P align=left><SPAN class=font10 lang=EN-US
12.0pt;font-family:宋體;color:black? mso-bidi-font-size:><IMG height=158
src="10分鐘學會PLD設計—2 編譯和布線.files/image061.jpg" width=324 border=0
v:shapes="_x0000_i1063"> <O:P></O:P></SPAN></P>
<P align=left><SPAN class=font10 font-family:宋體;color:black?
mso-bidi-font-size:12.0pt;>雙擊空白處，可以看到下圖所示<SPAN
lang=EN-US>IO在芯片EPM7128SLC84上的布局<O:P></O:P></SPAN></SPAN></P>
<P align=left><SPAN class=font10 lang=EN-US
12.0pt;font-family:宋體;color:black? mso-bidi-font-size:><IMG height=473
src="10分鐘學會PLD設計—2 編譯和布線.files/image063.jpg" width=553 border=0
v:shapes="_x0000_i1064"> <O:P></O:P></SPAN></P>
<P align=left><SPAN class=font10 lang=EN-US
mso-ansi-language:EN-US;mso-fareast-language:ZH-CN;mso-bidi-language:AR-SA?
Roman?;color:black;mso-font-kerning:1.0pt; New
宋體;mso-bidi-font-family:?Times
mso-bidi-font-size:12.0pt;font-family:><BR
style="PAGE-BREAK-BEFORE: always" clear=all></SPAN></P>
<P align=left><SPAN class=font10 lang=EN-US
12.0pt;font-family:宋體;color:black? mso-bidi-font-size:>創建一個設計的符號<SPAN
lang=EN-US><O:P></O:P></SPAN></SPAN></P>
<P align=left><SPAN class=font10 font-family:宋體?
mso-bidi-font-size:10.0pt;>（此和本設計無關，僅供其他設計在高層調用）</SPAN><SPAN
class=font10 lang=EN-US
mso-bidi-font-size:12.0pt;font-family:宋體?><O:P></O:P></SPAN></P>
<P align=left><SPAN class=font10
mso-bidi-font-size:10.0pt;font-family:宋體?>在</SPAN><SPAN class=font10
Arial? mso-bidi-font-size:10.0pt;font-family:宋體;mso-bidi-font-family:>
<SPAN lang=EN-US>File</SPAN></SPAN><SPAN class=font10
mso-bidi-font-size:10.0pt;font-family:宋體?>菜單中選擇</SPAN><SPAN class=font10
lang=EN-US Arial?
mso-bidi-font-size:10.0pt;font-family:宋體;mso-bidi-font-family:> Create
Default Symbol </SPAN><SPAN class=font10
mso-bidi-font-size:10.0pt;font-family:宋體?>項，即可創建一個設計的符號。該符號可被高層設計調用。<SPAN
lang=EN-US><O:P></O:P></SPAN></SPAN></P>
<P align=left><SPAN class=font10 lang=EN-US
mso-bidi-font-size:10.0pt;font-family:宋體?><IMG height=263
src="10分鐘學會PLD設計—2 編譯和布線.files/image064.jpg" width=352>
<O:P></O:P></SPAN></P>
<P align=left><SPAN class=font10
mso-bidi-font-size:10.0pt;font-family:宋體?>此時會產生一個<SPAN
lang=EN-US>COMPILE窗口，直接點Start,完成后點確認<O:P></O:P></SPAN></SPAN></P>
<P align=left><SPAN class=font10 lang=EN-US mso-bidi-font-size:
10.0pt;font-family:宋體?><IMG height=196
src="10分鐘學會PLD設計—2 編譯和布線.files/image067.jpg" width=553 border=0
v:shapes="_x0000_i1066"></SPAN></P>
<P align=left> </P>
<P align=left> </P>
<P align=left> </P>
<P class=font10 align=left>下面您可以繼續學習：</P>
<P class=font10 align=left><A class=font10
href="http://www.fpga.com.cn/rumen/simulation.htm">10分鐘學會PLD設計3
－設計的仿真</A></P>
<P class=font10 align=left><A class=font10
href="http://www.fpga.com.cn/rumen/download.htm">10分鐘學會PLD設計4
－下載</A></P>
<P align=left> </P></BLOCKQUOTE>
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