?? jk.vhd
字號:
--***************************************
--* JK Flip Flop (IF .. THEN .. ELSE) *
--* Filename : JK *
--***************************************
library IEEE;
use IEEE.std_logic_1164.all;
entity JK is
port (
J: in STD_LOGIC;
K: in STD_LOGIC;
CLK: in STD_LOGIC;
RESET: in STD_LOGIC;
Q: out STD_LOGIC;
Q_Bar: out STD_LOGIC
);
end JK;
architecture JK_arch of JK is
signal S:STD_LOGIC_VECTOR (1 downto 0);
signal Qout:STD_LOGIC;
begin
S <= J & k;
Process (CLK,RESET,Qout)
begin
if RESET = '1' then
Qout <= '0';
elsif CLK'event and CLK = '1' then
case S is
when "11" => Qout <= not Qout;
when "01" => Qout <= '0';
when "10" => Qout <= '1';
when others => null;
end case;
end if;
Q <= Qout;
Q_Bar <= not Qout;
end process;
end JK_arch;
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