?? dec2_4_c.vhd
字號:
--*********************************
--* 2 To 4 Decoder (CASE .. IS) *
--* Filename : DEC2_4_C *
--*********************************
library IEEE;
use IEEE.std_logic_1164.all;
entity DEC2_4_C is
port (
A: in STD_LOGIC_VECTOR (1 downto 0);
Y: out STD_LOGIC_VECTOR (0 to 3)
);
end DEC2_4_C;
architecture DEC2_4_C_arch of DEC2_4_C is
begin
process (A)
begin
case A is
when "00" => Y <= "0111";
when "01" => Y <= "1011";
when "10" => Y <= "1101";
when "11" => Y <= "1110";
when others => Y <= "1111";
end case;
end process;
end DEC2_4_C_arch;
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