?? usbtstpak.vhd
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--------------------------------------------------------------------------------
-- Copyright (c) 2000 by Trenz Electronic.
-- Duenner Kirchweg 77, 32257 Buende, Germany, www.trenz-electronic.de
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--------------------------------------------------------------------------------
-- Project: Full-Speed USB 1.1 Function Controller
-- File: usbTSTPAK.vhd
-- Description: USB testbench package.
-- Version: FB, 2000jun06
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package usbTSTPAK is
--------------------
component usbTSTctrl
port(
signal sim: in STD_LOGIC; -- TRUE while simulating
signal stim: in STD_LOGIC; -- TRUE to stimulate UUT
--
signal clk48: out STD_LOGIC; -- 48MHz clock
signal rst: out STD_LOGIC; -- async reset
--
signal uut_rxd: out STD_LOGIC; -- UUT rxd pin
signal uut_rx0: out STD_LOGIC; -- UUT rx0 pin
signal uut_txd: in STD_LOGIC; -- UUT txd pin
signal uut_tx0: in STD_LOGIC; -- UUT tx0 pin
--
signal tb_xd: in STD_LOGIC; -- testbench xd signal
signal tb_x0: in STD_LOGIC; -- testbench x0 signal
signal tb_clk: out STD_LOGIC -- testbench clock
);
end component;
--------------------
subtype packetCHR is STD_LOGIC_VECTOR(7 downto 0);
type packetBUF is array (POSITIVE range <>) of packetCHR;
procedure packetOUT(
signal clk: in STD_LOGIC;
signal xd: out STD_LOGIC;
signal x0: out STD_LOGIC;
addr: in STD_LOGIC_VECTOR(6 downto 0);
ep: in STD_LOGIC_VECTOR(3 downto 0));
procedure packetIN(
signal clk: in STD_LOGIC;
signal xd: out STD_LOGIC;
signal x0: out STD_LOGIC;
addr: in STD_LOGIC_VECTOR(6 downto 0);
ep: in STD_LOGIC_VECTOR(3 downto 0));
procedure packetSOF(
signal clk: in STD_LOGIC;
signal xd: out STD_LOGIC;
signal x0: out STD_LOGIC;
frame: in STD_LOGIC_VECTOR(10 downto 0));
procedure packetSETUP(
signal clk: in STD_LOGIC;
signal xd: out STD_LOGIC;
signal x0: out STD_LOGIC;
addr: in STD_LOGIC_VECTOR(6 downto 0);
ep: in STD_LOGIC_VECTOR(3 downto 0));
procedure packetDATA0(
signal clk: in STD_LOGIC;
signal xd: out STD_LOGIC;
signal x0: out STD_LOGIC;
data: in packetBUF);
procedure packetDATA0(
signal clk: in STD_LOGIC;
signal xd: out STD_LOGIC;
signal x0: out STD_LOGIC;
data: in packetCHR);
procedure packetDATA0(
signal clk: in STD_LOGIC;
signal xd: out STD_LOGIC;
signal x0: out STD_LOGIC);
procedure packetDATA1(
signal clk: in STD_LOGIC;
signal xd: out STD_LOGIC;
signal x0: out STD_LOGIC;
data: in packetBUF);
procedure packetDATA1(
signal clk: in STD_LOGIC;
signal xd: out STD_LOGIC;
signal x0: out STD_LOGIC;
data: in packetCHR);
procedure packetDATA1(
signal clk: in STD_LOGIC;
signal xd: out STD_LOGIC;
signal x0: out STD_LOGIC);
procedure packetACK(
signal clk: in STD_LOGIC;
signal xd: out STD_LOGIC;
signal x0: out STD_LOGIC);
procedure packetNAK(
signal clk: in STD_LOGIC;
signal xd: out STD_LOGIC;
signal x0: out STD_LOGIC);
procedure packetSTALL(
signal clk: in STD_LOGIC;
signal xd: out STD_LOGIC;
signal x0: out STD_LOGIC);
procedure packetIDLE(
signal clk: in STD_LOGIC;
signal xd: out STD_LOGIC;
signal x0: out STD_LOGIC;
cycles: in INTEGER);
procedure packetRESET(
signal clk: in STD_LOGIC;
signal xd: out STD_LOGIC;
signal x0: out STD_LOGIC);
end usbTSTPAK;
--------------------------------------------------------------------------------
package body usbTSTPAK is
-- token PIDs
constant fieldOUTpid: STD_LOGIC_VECTOR(7 downto 0):= "11100001";
constant fieldINpid: STD_LOGIC_VECTOR(7 downto 0):= "01101001";
constant fieldSOFpid: STD_LOGIC_VECTOR(7 downto 0):= "10100101";
constant fieldSETUPpid: STD_LOGIC_VECTOR(7 downto 0):= "00101101";
-- data PIDs
constant fieldDATA0pid: STD_LOGIC_VECTOR(7 downto 0):= "11000011";
constant fieldDATA1pid: STD_LOGIC_VECTOR(7 downto 0):= "01001011";
-- handshake PIDs
constant fieldACKpid: STD_LOGIC_VECTOR(7 downto 0):= "11010010";
constant fieldNAKpid: STD_LOGIC_VECTOR(7 downto 0):= "01011010";
constant fieldSTALLpid: STD_LOGIC_VECTOR(7 downto 0):= "00011110";
-- special PIDs
constant fieldPREpid: STD_LOGIC_VECTOR(7 downto 0):= "00111100";
-- CRC fields
constant fieldCRC5polynomial: STD_LOGIC_VECTOR(4 downto 0):= "00101";
constant fieldCRC5residual: STD_LOGIC_VECTOR(4 downto 0):= "01100";
constant fieldCRC16polynomial: STD_LOGIC_VECTOR(15 downto 0):= "1000000000000101";
constant fieldCRC16residual: STD_LOGIC_VECTOR(15 downto 0):= "1000000000001101";
-- internal variables
shared variable nrzi_x: STD_LOGIC;
shared variable nrzi_n: integer;
shared variable crc5: STD_LOGIC_VECTOR(4 downto 0);
shared variable crc16: STD_LOGIC_VECTOR(15 downto 0);
----------------------------------------
-- part #1: levels
procedure levelJ(
signal clk: in STD_LOGIC;
signal xd: out STD_LOGIC;
signal x0: out STD_LOGIC) is
begin
wait until rising_edge(clk);
xd<= '1';
x0<= '0';
end procedure;
--------------------
procedure levelK(
signal clk: in STD_LOGIC;
signal xd: out STD_LOGIC;
signal x0: out STD_LOGIC) is
begin
wait until rising_edge(clk);
xd<= '0';
x0<= '0';
end procedure;
--------------------
procedure levelSE0(
signal clk: in STD_LOGIC;
signal xd: out STD_LOGIC;
signal x0: out STD_LOGIC) is
begin
wait until rising_edge(clk);
xd<= '-';
x0<= '1';
end procedure;
--------------------
procedure levelD01(
signal clk: in STD_LOGIC;
signal xd: out STD_LOGIC;
signal x0: out STD_LOGIC;
d: in STD_LOGIC) is
begin
wait until rising_edge(clk);
xd<= d;
x0<= '0';
end procedure;
----------------------------------------
-- part #2: bits
procedure bitJ(
signal clk: in STD_LOGIC;
signal xd: out STD_LOGIC;
signal x0: out STD_LOGIC) is
begin
levelJ(clk, xd, x0);
nrzi_x:= '1';
nrzi_n:= 0;
end procedure;
--------------------
procedure bitK(
signal clk: in STD_LOGIC;
signal xd: out STD_LOGIC;
signal x0: out STD_LOGIC) is
begin
levelK(clk, xd, x0);
nrzi_x:= '0';
nrzi_n:= 0;
end procedure;
--------------------
procedure bitSE0(
signal clk: in STD_LOGIC;
signal xd: out STD_LOGIC;
signal x0: out STD_LOGIC) is
begin
levelSE0(clk, xd, x0);
nrzi_x:= 'X';
nrzi_n:= 0;
end procedure;
--------------------
procedure bit01(
signal clk: in STD_LOGIC;
signal xd: out STD_LOGIC;
signal x0: out STD_LOGIC;
d: in STD_LOGIC) is
begin
if d= '0' then
levelD01(clk, xd, x0, not(nrzi_x)); -- zero: toggle
nrzi_x:= not(nrzi_x);
nrzi_n:= 0;
elsif d= '1' then
levelD01(clk, xd, x0, nrzi_x); -- one: keep value
nrzi_n:= nrzi_n + 1;
if nrzi_n= 6 then
levelD01(clk, xd, x0, not(nrzi_x)); -- bitstuff: toggle
nrzi_x:= not(nrzi_x);
nrzi_n:= 0;
end if;
else
levelD01(clk, xd, x0, 'X'); -- undefined
nrzi_x:= 'X';
nrzi_n:= 0;
end if;
end procedure;
----------------------------------------
-- part #3: fields
procedure fieldComputeCRC5(d: in STD_LOGIC) is
variable q: STD_LOGIC;
begin
-- For CRC generation and checking, the shift registers in the
-- generator and checker are seeded with an all-ones pattern.
-- For each data bit sent or received, the high order bit of
-- the current remainder is XORed with the data bit and then
-- the remainder is shifted left one bit and the low-order bit
-- set to zero. If the result of that XOR is one, then the
-- remainder is XORed with the generator polynomial.
q:= crc5(crc5'left) xor d;
crc5:= crc5(crc5'left-1 downto 0) & '0';
if q= '1' then
crc5:= crc5 xor fieldCRC5polynomial;
end if;
end procedure;
--------------------
procedure fieldComputeCRC16(d: in STD_LOGIC) is
variable q: STD_LOGIC;
begin
q:= crc16(crc16'left) xor d;
crc16:= crc16(crc16'left-1 downto 0) & '0';
if q= '1' then
crc16:= crc16 xor fieldCRC16polynomial;
end if;
end procedure;
--------------------
procedure fieldSYNC(
signal clk: in STD_LOGIC;
signal xd: out STD_LOGIC;
signal x0: out STD_LOGIC) is
begin
bitK(clk, xd, x0);
bitJ(clk, xd, x0);
bitK(clk, xd, x0);
bitJ(clk, xd, x0);
bitK(clk, xd, x0);
bitJ(clk, xd, x0);
bitK(clk, xd, x0);
bitK(clk, xd, x0);
end procedure;
--------------------
procedure fieldEOP(
signal clk: in STD_LOGIC;
signal xd: out STD_LOGIC;
signal x0: out STD_LOGIC) is
begin
bitSE0(clk, xd, x0);
bitSE0(clk, xd, x0);
bitJ (clk, xd, x0);
end procedure;
--------------------
procedure fieldIDLE(
signal clk: in STD_LOGIC;
signal xd: out STD_LOGIC;
signal x0: out STD_LOGIC) is
begin
bitJ (clk, xd, x0);
end procedure;
--------------------
procedure fieldSE0(
signal clk: in STD_LOGIC;
signal xd: out STD_LOGIC;
signal x0: out STD_LOGIC) is
begin
bitSE0(clk, xd, x0);
end procedure;
--------------------
procedure fieldADDR(
signal clk: in STD_LOGIC;
signal xd: out STD_LOGIC;
signal x0: out STD_LOGIC;
addr: in STD_LOGIC_VECTOR(6 downto 0)) is
begin
bit01(clk, xd, x0, addr(0)); fieldComputeCRC5(addr(0));
bit01(clk, xd, x0, addr(1)); fieldComputeCRC5(addr(1));
bit01(clk, xd, x0, addr(2)); fieldComputeCRC5(addr(2));
bit01(clk, xd, x0, addr(3)); fieldComputeCRC5(addr(3));
bit01(clk, xd, x0, addr(4)); fieldComputeCRC5(addr(4));
bit01(clk, xd, x0, addr(5)); fieldComputeCRC5(addr(5));
bit01(clk, xd, x0, addr(6)); fieldComputeCRC5(addr(6));
end procedure;
--------------------
procedure fieldEP(
signal clk: in STD_LOGIC;
signal xd: out STD_LOGIC;
signal x0: out STD_LOGIC;
ep: in STD_LOGIC_VECTOR(3 downto 0)) is
begin
bit01(clk, xd, x0, ep(0)); fieldComputeCRC5(ep(0));
bit01(clk, xd, x0, ep(1)); fieldComputeCRC5(ep(1));
bit01(clk, xd, x0, ep(2)); fieldComputeCRC5(ep(2));
bit01(clk, xd, x0, ep(3)); fieldComputeCRC5(ep(3));
end procedure;
--------------------
procedure fieldFRAME(
signal clk: in STD_LOGIC;
signal xd: out STD_LOGIC;
signal x0: out STD_LOGIC;
frame: in STD_LOGIC_VECTOR(10 downto 0)) is
begin
bit01(clk, xd, x0, frame(0)); fieldComputeCRC5(frame(0));
bit01(clk, xd, x0, frame(1)); fieldComputeCRC5(frame(1));
bit01(clk, xd, x0, frame(2)); fieldComputeCRC5(frame(2));
bit01(clk, xd, x0, frame(3)); fieldComputeCRC5(frame(3));
bit01(clk, xd, x0, frame(4)); fieldComputeCRC5(frame(4));
bit01(clk, xd, x0, frame(5)); fieldComputeCRC5(frame(5));
bit01(clk, xd, x0, frame(6)); fieldComputeCRC5(frame(6));
bit01(clk, xd, x0, frame(7)); fieldComputeCRC5(frame(7));
bit01(clk, xd, x0, frame(8)); fieldComputeCRC5(frame(8));
bit01(clk, xd, x0, frame(9)); fieldComputeCRC5(frame(9));
bit01(clk, xd, x0, frame(10)); fieldComputeCRC5(frame(10));
end procedure;
--------------------
procedure fieldPID(
signal clk: in STD_LOGIC;
signal xd: out STD_LOGIC;
signal x0: out STD_LOGIC;
data: in STD_LOGIC_VECTOR(7 downto 0)) is
begin
bit01(clk, xd, x0, data(0));
bit01(clk, xd, x0, data(1));
bit01(clk, xd, x0, data(2));
bit01(clk, xd, x0, data(3));
bit01(clk, xd, x0, data(4));
bit01(clk, xd, x0, data(5));
bit01(clk, xd, x0, data(6));
bit01(clk, xd, x0, data(7));
crc5:= (others=> '1');
crc16:= (others=> '1');
end procedure;
--------------------
procedure fieldBYTE(
signal clk: in STD_LOGIC;
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