?? de2_lcm_ccd.pin
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-- Copyright (C) 1991-2008 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--
-- This is a Quartus II output file. It is for reporting purposes only, and is
-- not intended for use as a Quartus II input file. This file cannot be used
-- to make Quartus II pin assignments - for instructions on how to make pin
-- assignments, please see Quartus II help.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- NC : No Connect. This pin has no internal connection to the device.
-- DNU : Do Not Use. This pin MUST NOT be connected.
-- VCCPGM : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V or 3.0V depending on the needs of the configuration device.
-- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
-- of its bank.
-- Bank 1: 3.3V
-- Bank 2: 3.3V
-- Bank 3: 3.3V
-- Bank 4: 3.3V
-- Bank 5: 3.3V
-- Bank 6: 3.3V
-- Bank 7: 3.3V
-- Bank 8: 3.3V
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
-- It can also be used to report unused dedicated pins. The connection
-- on the board for unused dedicated pins depends on whether this will
-- be used in a future design. One example is device migration. When
-- using device migration, refer to the device pin-tables. If it is a
-- GND pin in the pin table or if it will not be used in a future design
-- for another purpose the it MUST be connected to GND. If it is an unused
-- dedicated pin, then it can be connected to a valid signal on the board
-- (low, high, or toggling) if that signal is required for a different
-- revision of the design.
-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
-- This pin should be connected to GND. It may also be connected to a
-- valid signal on the board (low, high, or toggling) if that signal
-- is required for a different revision of the design.
-- GND* : Unused I/O pin. For transceiver I/O banks (Bank 13, 14, 15, 16 and 17),
-- connect each pin marked GND* either individually through a 10 kohm resistor
-- to GND or tie all pins together and connect through a single 10 kohm resistor
-- to GND.
-- For non-transceiver I/O banks, connect each pin marked GND* directly to GND
-- or leave it unconnected.
-- RESERVED : Unused I/O pin, which MUST be left unconnected.
-- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
-- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
-- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
-- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- Pin directions (input, output or bidir) are based on device operating in user mode.
---------------------------------------------------------------------------------
Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version
CHIP "DE2_LCM_CCD" ASSIGNED TO AN: EP2C35F672C6
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
-------------------------------------------------------------------------------------------------------------
GND : A2 : gnd : : : :
VCCIO3 : A3 : power : : 3.3V : 3 :
AUD_DACDAT : A4 : output : 3.3-V LVTTL : : 3 : Y
AUD_XCK : A5 : output : 3.3-V LVTTL : : 3 : Y
I2C_SCLK : A6 : output : 3.3-V LVTTL : : 3 : Y
VGA_HS : A7 : output : 3.3-V LVTTL : : 3 : Y
VGA_R[5] : A8 : output : 3.3-V LVTTL : : 3 : Y
VGA_G[1] : A9 : output : 3.3-V LVTTL : : 3 : Y
VGA_G[5] : A10 : output : 3.3-V LVTTL : : 3 : Y
VCCIO3 : A11 : power : : 3.3V : 3 :
GND : A12 : gnd : : : :
SW[9] : A13 : input : 3.3-V LVTTL : : 4 : Y
TCS : A14 : input : 3.3-V LVTTL : : 4 : Y
GND : A15 : gnd : : : :
VCCIO4 : A16 : power : : 3.3V : 4 :
ENET_DATA[5] : A17 : bidir : 3.3-V LVTTL : : 4 : Y
ENET_DATA[3] : A18 : bidir : 3.3-V LVTTL : : 4 : Y
ENET_DATA[13] : A19 : bidir : 3.3-V LVTTL : : 4 : Y
ENET_DATA[9] : A20 : bidir : 3.3-V LVTTL : : 4 : Y
ENET_CMD : A21 : output : 3.3-V LVTTL : : 4 : Y
ENET_RD_N : A22 : output : 3.3-V LVTTL : : 4 : Y
ENET_CS_N : A23 : output : 3.3-V LVTTL : : 4 : Y
VCCIO4 : A24 : power : : 3.3V : 4 :
GND : A25 : gnd : : : :
DRAM_DQ[2] : AA1 : bidir : 3.3-V LVTTL : : 1 : Y
DRAM_DQ[1] : AA2 : bidir : 3.3-V LVTTL : : 1 : Y
DRAM_DQ[12] : AA3 : bidir : 3.3-V LVTTL : : 1 : Y
DRAM_DQ[11] : AA4 : bidir : 3.3-V LVTTL : : 1 : Y
DRAM_DQ[15] : AA5 : bidir : 3.3-V LVTTL : : 1 : Y
DRAM_CKE : AA6 : output : 3.3-V LVTTL : : 1 : Y
DRAM_CLK : AA7 : output : 3.3-V LVTTL : : 1 : Y
VCCA_PLL1 : AA8 : power : : 1.2V : :
SRAM_DQ[3] : AA9 : bidir : 3.3-V LVTTL : : 8 : Y
SRAM_DQ[4] : AA10 : bidir : 3.3-V LVTTL : : 8 : Y
SRAM_DQ[6] : AA11 : bidir : 3.3-V LVTTL : : 8 : Y
RESERVED_INPUT : AA12 : : : : 8 :
LEDR[10] : AA13 : output : 3.3-V LVTTL : : 7 : Y
LEDR[8] : AA14 : output : 3.3-V LVTTL : : 7 : Y
FL_ADDR[19] : AA15 : output : 3.3-V LVTTL : : 7 : Y
FL_ADDR[7] : AA16 : output : 3.3-V LVTTL : : 7 : Y
FL_WE_N : AA17 : output : 3.3-V LVTTL : : 7 : Y
FL_RST_N : AA18 : output : 3.3-V LVTTL : : 7 : Y
VCCA_PLL4 : AA19 : power : : 1.2V : :
LEDG[6] : AA20 : output : 3.3-V LVTTL : : 7 : Y
GND_PLL4 : AA21 : gnd : : : :
VCCIO6 : AA22 : power : : 3.3V : 6 :
HEX1[5] : AA23 : output : 3.3-V LVTTL : : 6 : Y
HEX1[4] : AA24 : output : 3.3-V LVTTL : : 6 : Y
HEX3[1] : AA25 : output : 3.3-V LVTTL : : 6 : Y
HEX3[2] : AA26 : output : 3.3-V LVTTL : : 6 : Y
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