?? count.tan.qmsg
字號:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register count_int\[7\] register count_int\[7\] 185.36 MHz 5.395 ns Internal " "Info: Clock \"clk\" has Internal fmax of 185.36 MHz between source register \"count_int\[7\]\" and destination register \"count_int\[7\]\" (period= 5.395 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.131 ns + Longest register register " "Info: + Longest register to register delay is 5.131 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count_int\[7\] 1 REG LCFF_X16_Y11_N21 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X16_Y11_N21; Fanout = 3; REG Node = 'count_int\[7\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { count_int[7] } "NODE_NAME" } } { "count.vhd" "" { Text "E:/tool_stud/vhdl/count.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.481 ns) + CELL(0.651 ns) 1.132 ns Equal0~284 2 COMB LCCOMB_X16_Y11_N4 1 " "Info: 2: + IC(0.481 ns) + CELL(0.651 ns) = 1.132 ns; Loc. = LCCOMB_X16_Y11_N4; Fanout = 1; COMB Node = 'Equal0~284'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.132 ns" { count_int[7] Equal0~284 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.651 ns) 2.874 ns Equal0~287 3 COMB LCCOMB_X16_Y10_N30 2 " "Info: 3: + IC(1.091 ns) + CELL(0.651 ns) = 2.874 ns; Loc. = LCCOMB_X16_Y10_N30; Fanout = 2; COMB Node = 'Equal0~287'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.742 ns" { Equal0~284 Equal0~287 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.373 ns) + CELL(0.206 ns) 3.453 ns count_int\[2\]~474 4 COMB LCCOMB_X16_Y10_N28 27 " "Info: 4: + IC(0.373 ns) + CELL(0.206 ns) = 3.453 ns; Loc. = LCCOMB_X16_Y10_N28; Fanout = 27; COMB Node = 'count_int\[2\]~474'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.579 ns" { Equal0~287 count_int[2]~474 } "NODE_NAME" } } { "count.vhd" "" { Text "E:/tool_stud/vhdl/count.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.018 ns) + CELL(0.660 ns) 5.131 ns count_int\[7\] 5 REG LCFF_X16_Y11_N21 3 " "Info: 5: + IC(1.018 ns) + CELL(0.660 ns) = 5.131 ns; Loc. = LCFF_X16_Y11_N21; Fanout = 3; REG Node = 'count_int\[7\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.678 ns" { count_int[2]~474 count_int[7] } "NODE_NAME" } } { "count.vhd" "" { Text "E:/tool_stud/vhdl/count.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.168 ns ( 42.25 % ) " "Info: Total cell delay = 2.168 ns ( 42.25 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.963 ns ( 57.75 % ) " "Info: Total interconnect delay = 2.963 ns ( 57.75 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.131 ns" { count_int[7] Equal0~284 Equal0~287 count_int[2]~474 count_int[7] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.131 ns" { count_int[7] Equal0~284 Equal0~287 count_int[2]~474 count_int[7] } { 0.000ns 0.481ns 1.091ns 0.373ns 1.018ns } { 0.000ns 0.651ns 0.651ns 0.206ns 0.660ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.843 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.843 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "count.vhd" "" { Text "E:/tool_stud/vhdl/count.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 28 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 28; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "count.vhd" "" { Text "E:/tool_stud/vhdl/count.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.898 ns) + CELL(0.666 ns) 2.843 ns count_int\[7\] 3 REG LCFF_X16_Y11_N21 3 " "Info: 3: + IC(0.898 ns) + CELL(0.666 ns) = 2.843 ns; Loc. = LCFF_X16_Y11_N21; Fanout = 3; REG Node = 'count_int\[7\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.564 ns" { clk~clkctrl count_int[7] } "NODE_NAME" } } { "count.vhd" "" { Text "E:/tool_stud/vhdl/count.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.52 % ) " "Info: Total cell delay = 1.806 ns ( 63.52 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.037 ns ( 36.48 % ) " "Info: Total interconnect delay = 1.037 ns ( 36.48 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.843 ns" { clk clk~clkctrl count_int[7] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.843 ns" { clk clk~combout clk~clkctrl count_int[7] } { 0.000ns 0.000ns 0.139ns 0.898ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.843 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.843 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "count.vhd" "" { Text "E:/tool_stud/vhdl/count.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 28 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 28; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "count.vhd" "" { Text "E:/tool_stud/vhdl/count.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.898 ns) + CELL(0.666 ns) 2.843 ns count_int\[7\] 3 REG LCFF_X16_Y11_N21 3 " "Info: 3: + IC(0.898 ns) + CELL(0.666 ns) = 2.843 ns; Loc. = LCFF_X16_Y11_N21; Fanout = 3; REG Node = 'count_int\[7\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.564 ns" { clk~clkctrl count_int[7] } "NODE_NAME" } } { "count.vhd" "" { Text "E:/tool_stud/vhdl/count.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.52 % ) " "Info: Total cell delay = 1.806 ns ( 63.52 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.037 ns ( 36.48 % ) " "Info: Total interconnect delay = 1.037 ns ( 36.48 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.843 ns" { clk clk~clkctrl count_int[7] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.843 ns" { clk clk~combout clk~clkctrl count_int[7] } { 0.000ns 0.000ns 0.139ns 0.898ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.843 ns" { clk clk~clkctrl count_int[7] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.843 ns" { clk clk~combout clk~clkctrl count_int[7] } { 0.000ns 0.000ns 0.139ns 0.898ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.843 ns" { clk clk~clkctrl count_int[7] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.843 ns" { clk clk~combout clk~clkctrl count_int[7] } { 0.000ns 0.000ns 0.139ns 0.898ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "count.vhd" "" { Text "E:/tool_stud/vhdl/count.vhd" 30 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "count.vhd" "" { Text "E:/tool_stud/vhdl/count.vhd" 30 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.131 ns" { count_int[7] Equal0~284 Equal0~287 count_int[2]~474 count_int[7] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.131 ns" { count_int[7] Equal0~284 Equal0~287 count_int[2]~474 count_int[7] } { 0.000ns 0.481ns 1.091ns 0.373ns 1.018ns } { 0.000ns 0.651ns 0.651ns 0.206ns 0.660ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.843 ns" { clk clk~clkctrl count_int[7] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.843 ns" { clk clk~combout clk~clkctrl count_int[7] } { 0.000ns 0.000ns 0.139ns 0.898ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.843 ns" { clk clk~clkctrl count_int[7] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.843 ns" { clk clk~combout clk~clkctrl count_int[7] } { 0.000ns 0.000ns 0.139ns 0.898ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "count_int\[7\] reset clk 6.685 ns register " "Info: tsu for register \"count_int\[7\]\" (data pin = \"reset\", clock pin = \"clk\") is 6.685 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.568 ns + Longest pin register " "Info: + Longest pin to register delay is 9.568 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.954 ns) 0.954 ns reset 1 PIN PIN_185 2 " "Info: 1: + IC(0.000 ns) + CELL(0.954 ns) = 0.954 ns; Loc. = PIN_185; Fanout = 2; PIN Node = 'reset'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "count.vhd" "" { Text "E:/tool_stud/vhdl/count.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.312 ns) + CELL(0.624 ns) 7.890 ns count_int\[2\]~474 2 COMB LCCOMB_X16_Y10_N28 27 " "Info: 2: + IC(6.312 ns) + CELL(0.624 ns) = 7.890 ns; Loc. = LCCOMB_X16_Y10_N28; Fanout = 27; COMB Node = 'count_int\[2\]~474'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.936 ns" { reset count_int[2]~474 } "NODE_NAME" } } { "count.vhd" "" { Text "E:/tool_stud/vhdl/count.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.018 ns) + CELL(0.660 ns) 9.568 ns count_int\[7\] 3 REG LCFF_X16_Y11_N21 3 " "Info: 3: + IC(1.018 ns) + CELL(0.660 ns) = 9.568 ns; Loc. = LCFF_X16_Y11_N21; Fanout = 3; REG Node = 'count_int\[7\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.678 ns" { count_int[2]~474 count_int[7] } "NODE_NAME" } } { "count.vhd" "" { Text "E:/tool_stud/vhdl/count.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.238 ns ( 23.39 % ) " "Info: Total cell delay = 2.238 ns ( 23.39 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.330 ns ( 76.61 % ) " "Info: Total interconnect delay = 7.330 ns ( 76.61 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.568 ns" { reset count_int[2]~474 count_int[7] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "9.568 ns" { reset reset~combout count_int[2]~474 count_int[7] } { 0.000ns 0.000ns 6.312ns 1.018ns } { 0.000ns 0.954ns 0.624ns 0.660ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "count.vhd" "" { Text "E:/tool_stud/vhdl/count.vhd" 30 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.843 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.843 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "count.vhd" "" { Text "E:/tool_stud/vhdl/count.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 28 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 28; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "count.vhd" "" { Text "E:/tool_stud/vhdl/count.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.898 ns) + CELL(0.666 ns) 2.843 ns count_int\[7\] 3 REG LCFF_X16_Y11_N21 3 " "Info: 3: + IC(0.898 ns) + CELL(0.666 ns) = 2.843 ns; Loc. = LCFF_X16_Y11_N21; Fanout = 3; REG Node = 'count_int\[7\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.564 ns" { clk~clkctrl count_int[7] } "NODE_NAME" } } { "count.vhd" "" { Text "E:/tool_stud/vhdl/count.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.52 % ) " "Info: Total cell delay = 1.806 ns ( 63.52 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.037 ns ( 36.48 % ) " "Info: Total interconnect delay = 1.037 ns ( 36.48 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.843 ns" { clk clk~clkctrl count_int[7] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.843 ns" { clk clk~combout clk~clkctrl count_int[7] } { 0.000ns 0.000ns 0.139ns 0.898ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.568 ns" { reset count_int[2]~474 count_int[7] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "9.568 ns" { reset reset~combout count_int[2]~474 count_int[7] } { 0.000ns 0.000ns 6.312ns 1.018ns } { 0.000ns 0.954ns 0.624ns 0.660ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.843 ns" { clk clk~clkctrl count_int[7] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.843 ns" { clk clk~combout clk~clkctrl count_int[7] } { 0.000ns 0.000ns 0.139ns 0.898ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk plus_1s plus_1s~reg0 8.195 ns register " "Info: tco from clock \"clk\" to destination pin \"plus_1s\" through register \"plus_1s~reg0\" is 8.195 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.820 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.820 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "count.vhd" "" { Text "E:/tool_stud/vhdl/count.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 28 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 28; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "count.vhd" "" { Text "E:/tool_stud/vhdl/count.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.875 ns) + CELL(0.666 ns) 2.820 ns plus_1s~reg0 3 REG LCFF_X15_Y10_N1 1 " "Info: 3: + IC(0.875 ns) + CELL(0.666 ns) = 2.820 ns; Loc. = LCFF_X15_Y10_N1; Fanout = 1; REG Node = 'plus_1s~reg0'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.541 ns" { clk~clkctrl plus_1s~reg0 } "NODE_NAME" } } { "count.vhd" "" { Text "E:/tool_stud/vhdl/count.vhd" 44 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.04 % ) " "Info: Total cell delay = 1.806 ns ( 64.04 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.014 ns ( 35.96 % ) " "Info: Total interconnect delay = 1.014 ns ( 35.96 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.820 ns" { clk clk~clkctrl plus_1s~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.820 ns" { clk clk~combout clk~clkctrl plus_1s~reg0 } { 0.000ns 0.000ns 0.139ns 0.875ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "count.vhd" "" { Text "E:/tool_stud/vhdl/count.vhd" 44 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.071 ns + Longest register pin " "Info: + Longest register to pin delay is 5.071 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns plus_1s~reg0 1 REG LCFF_X15_Y10_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X15_Y10_N1; Fanout = 1; REG Node = 'plus_1s~reg0'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { plus_1s~reg0 } "NODE_NAME" } } { "count.vhd" "" { Text "E:/tool_stud/vhdl/count.vhd" 44 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.795 ns) + CELL(3.276 ns) 5.071 ns plus_1s 2 PIN PIN_189 0 " "Info: 2: + IC(1.795 ns) + CELL(3.276 ns) = 5.071 ns; Loc. = PIN_189; Fanout = 0; PIN Node = 'plus_1s'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.071 ns" { plus_1s~reg0 plus_1s } "NODE_NAME" } } { "count.vhd" "" { Text "E:/tool_stud/vhdl/count.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.276 ns ( 64.60 % ) " "Info: Total cell delay = 3.276 ns ( 64.60 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.795 ns ( 35.40 % ) " "Info: Total interconnect delay = 1.795 ns ( 35.40 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.071 ns" { plus_1s~reg0 plus_1s } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.071 ns" { plus_1s~reg0 plus_1s } { 0.000ns 1.795ns } { 0.000ns 3.276ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.820 ns" { clk clk~clkctrl plus_1s~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.820 ns" { clk clk~combout clk~clkctrl plus_1s~reg0 } { 0.000ns 0.000ns 0.139ns 0.875ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.071 ns" { plus_1s~reg0 plus_1s } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.071 ns" { plus_1s~reg0 plus_1s } { 0.000ns 1.795ns } { 0.000ns 3.276ns } } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "plus_1s~reg0 reset clk -5.148 ns register " "Info: th for register \"plus_1s~reg0\" (data pin = \"reset\", clock pin = \"clk\") is -5.148 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.820 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.820 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "count.vhd" "" { Text "E:/tool_stud/vhdl/count.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 28 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 28; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "count.vhd" "" { Text "E:/tool_stud/vhdl/count.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.875 ns) + CELL(0.666 ns) 2.820 ns plus_1s~reg0 3 REG LCFF_X15_Y10_N1 1 " "Info: 3: + IC(0.875 ns) + CELL(0.666 ns) = 2.820 ns; Loc. = LCFF_X15_Y10_N1; Fanout = 1; REG Node = 'plus_1s~reg0'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.541 ns" { clk~clkctrl plus_1s~reg0 } "NODE_NAME" } } { "count.vhd" "" { Text "E:/tool_stud/vhdl/count.vhd" 44 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.04 % ) " "Info: Total cell delay = 1.806 ns ( 64.04 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.014 ns ( 35.96 % ) " "Info: Total interconnect delay = 1.014 ns ( 35.96 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.820 ns" { clk clk~clkctrl plus_1s~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.820 ns" { clk clk~combout clk~clkctrl plus_1s~reg0 } { 0.000ns 0.000ns 0.139ns 0.875ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" { } { { "count.vhd" "" { Text "E:/tool_stud/vhdl/count.vhd" 44 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.274 ns - Shortest pin register " "Info: - Shortest pin to register delay is 8.274 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.954 ns) 0.954 ns reset 1 PIN PIN_185 2 " "Info: 1: + IC(0.000 ns) + CELL(0.954 ns) = 0.954 ns; Loc. = PIN_185; Fanout = 2; PIN Node = 'reset'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "count.vhd" "" { Text "E:/tool_stud/vhdl/count.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.678 ns) + CELL(0.534 ns) 8.166 ns plus_1s~4 2 COMB LCCOMB_X15_Y10_N0 1 " "Info: 2: + IC(6.678 ns) + CELL(0.534 ns) = 8.166 ns; Loc. = LCCOMB_X15_Y10_N0; Fanout = 1; COMB Node = 'plus_1s~4'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.212 ns" { reset plus_1s~4 } "NODE_NAME" } } { "count.vhd" "" { Text "E:/tool_stud/vhdl/count.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 8.274 ns plus_1s~reg0 3 REG LCFF_X15_Y10_N1 1 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 8.274 ns; Loc. = LCFF_X15_Y10_N1; Fanout = 1; REG Node = 'plus_1s~reg0'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.108 ns" { plus_1s~4 plus_1s~reg0 } "NODE_NAME" } } { "count.vhd" "" { Text "E:/tool_stud/vhdl/count.vhd" 44 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.596 ns ( 19.29 % ) " "Info: Total cell delay = 1.596 ns ( 19.29 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.678 ns ( 80.71 % ) " "Info: Total interconnect delay = 6.678 ns ( 80.71 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.274 ns" { reset plus_1s~4 plus_1s~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.274 ns" { reset reset~combout plus_1s~4 plus_1s~reg0 } { 0.000ns 0.000ns 6.678ns 0.000ns } { 0.000ns 0.954ns 0.534ns 0.108ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.820 ns" { clk clk~clkctrl plus_1s~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.820 ns" { clk clk~combout clk~clkctrl plus_1s~reg0 } { 0.000ns 0.000ns 0.139ns 0.875ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.274 ns" { reset plus_1s~4 plus_1s~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.274 ns" { reset reset~combout plus_1s~4 plus_1s~reg0 } { 0.000ns 0.000ns 6.678ns 0.000ns } { 0.000ns 0.954ns 0.534ns 0.108ns } } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
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