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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 4.616 ns
From           : rst
To             : lcd:inst1|clkcnt[3]
From Clock     : 
To Clock       : mclk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 24.142 ns
From           : lcd:inst1|lcd_rs
To             : lcd_rs
From Clock     : mclk
To Clock       : 
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 2.901 ns
From           : altera_internal_jtag~TDO
To             : altera_reserved_tdo
From Clock     : 
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 6.819 ns
From           : rst
To             : lcd:inst1|lcd_rs
From Clock     : 
To Clock       : mclk
Failed Paths   : 0

Type           : Clock Setup: 'mclk'
Slack          : N/A
Required Time  : None
Actual Time    : 56.58 MHz ( period = 17.674 ns )
From           : lcd:inst1|lcd_e
To             : sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[14]
From Clock     : mclk
To Clock       : mclk
Failed Paths   : 0

Type           : Clock Setup: 'altera_internal_jtag~TCKUTAP'
Slack          : N/A
Required Time  : None
Actual Time    : 95.20 MHz ( period = 10.504 ns )
From           : sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:info_data_shift_out|dffs[0]
To             : sld_hub:sld_hub_inst|hub_tdo
From Clock     : altera_internal_jtag~TCKUTAP
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Hold: 'mclk'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : lcd:inst1|state.WRITERAM
To             : lcd:inst1|state.WRITERAM
From Clock     : mclk
To Clock       : mclk
Failed Paths   : 12

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 12

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