?? add_sub_9mh.tdf
字號(hào):
--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone II" LPM_DIRECTION="ADD" LPM_PIPELINE=1 LPM_WIDTH=16 ONE_INPUT_IS_CONSTANT="NO" aclr clken clock dataa datab result
--VERSION_BEGIN 7.1 cbx_cycloneii 2007:01:23:09:39:40:SJ cbx_lpm_add_sub 2007:01:08:11:15:18:SJ cbx_mgl 2007:04:03:14:06:46:SJ cbx_stratix 2007:04:12:16:43:52:SJ cbx_stratixii 2007:02:12:17:08:26:SJ VERSION_END
-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--synthesis_resources = lut 16
SUBDESIGN add_sub_9mh
(
aclr : input;
clken : input;
clock : input;
dataa[15..0] : input;
datab[15..0] : input;
result[15..0] : output;
)
VARIABLE
pipeline_dffe[15..0] : DFFE;
result_int[15..0] : WIRE;
BEGIN
result_int[] = dataa[] + datab[];
pipeline_dffe[].clk = clock;
pipeline_dffe[].clrn = !aclr;
pipeline_dffe[].ena = clken;
result[] = pipeline_dffe[15..0].q;
pipeline_dffe[15..0].d = result_int[];
END;
--VALID FILE
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