?? fenping2.vhd
字號:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fenping2 is
port(clk_4m:in std_logic;
clk2,clk3:out std_logic);
end;
architecture art of fenping2 is
signal cp2 ,cp3 :std_logic;
signal count:std_logic_vector(15 downto 0);
signal s: std_logic_vector(15 downto 0);
begin
process(clk_4m) is
begin
if(clk_4m'event and clk_4m='1') then
if count="0000000000001000" then
count<=(others=>'0');cp2<=not cp2;
else count<=count+1;
end if;
end if;
clk2<=cp2;
end process;
process(cp2) is
begin
if(cp2'event and cp2='1') then
if s="0000000000000010" then
s<=(others=>'0');cp3<=not cp3;
else s<=s+1;
end if;
end if;
clk3<=cp3;
end process;
end;
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