library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity  control is
 port(p0:in std_logic_vector(7 downto 0);
      ale:in std_logic;
      wr:in std_logic;
       a:in std_logic_vector(3 downto 0);
       sel :out std_logic_vector(3 downto 0);
       dataout:out std_logic_vector(7 downto 0));
end;
architecture art of control is
 signal s:std_logic_vector(3 downto 0);
 signal data:std_logic_vector(7 downto 0);
  begin
process(ale)
begin
  if ale'event and ale='1' then
        data<=p0;
  end if;
     end process;
 process(wr)
  begin
      if wr'event and wr='1' then
          s<=a;
     end if;
  end process;  
  sel<=s;
 dataout<=data;
end ;