?? std_1s40.ptf
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SYSTEM std_1s40
{
System_Wizard_Version = "5.00";
System_Wizard_Build = "146";
WIZARD_SCRIPT_ARGUMENTS
{
device_family = "STRATIX";
clock_freq = "50000000";
generate_hdl = "1";
generate_sdk = "0";
do_build_sim = "0";
hdl_language = "verilog";
view_master_columns = "1";
view_master_priorities = "0";
board_class = "altera_nios_dev_board_stratix_1s40";
name_column_width = "344";
desc_column_width = "344";
bustype_column_width = "0";
base_column_width = "75";
end_column_width = "75";
view_frame_window = "32:32:1232:811";
do_log_history = "0";
device_family_id = "STRATIX";
CLOCKS
{
clk = "50000000";
}
clock_column_width = "73";
BOARD_INFO
{
CONFIGURATION factory
{
length = "";
menu_position = "2";
offset = "0x600000";
reference_designator = "U5";
}
CONFIGURATION user
{
length = "";
menu_position = "1";
offset = "0x400000";
reference_designator = "U5";
}
JTAG_device_index = "1";
REFDES U5
{
base = "0x00800000";
}
altera_avalon_cfi_flash
{
reference_designators = "U5";
}
class = "altera_nios_dev_board_stratix_1s40";
class_version = "5.0";
device_family = "STRATIX";
quartus_pgm_file = "system/altera_nios_dev_board_stratix_1s40.sof";
quartus_project_file = "system/altera_nios_dev_board_stratix_1s40.qpf";
reference_designators = "U5";
sopc_system_file = "system/altera_nios_dev_board_stratix_1s40.ptf";
}
hardcopy_compatible = "0";
}
MODULE cpu
{
class = "altera_nios2";
class_version = "5.0";
iss_model_name = "altera_nios2";
HDL_INFO
{
PLI_Files = "";
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/cpu_test_bench.v, __PROJECT_DIRECTORY__/cpu_mult_cell.v, __PROJECT_DIRECTORY__/cpu_jtag_debug_module.v, __PROJECT_DIRECTORY__/cpu_jtag_debug_module_wrapper.v, __PROJECT_DIRECTORY__/cpu.v";
Synthesis_Only_Files = "";
}
MASTER instruction_master
{
PORT_WIRING
{
PORT i_address
{
direction = "output";
type = "address";
width = "26";
Is_Enabled = "1";
}
PORT i_read
{
direction = "output";
type = "read";
width = "1";
Is_Enabled = "1";
}
PORT i_readdata
{
direction = "input";
type = "readdata";
width = "32";
Is_Enabled = "1";
}
PORT i_readdatavalid
{
direction = "input";
type = "readdatavalid";
width = "1";
Is_Enabled = "1";
}
PORT i_waitrequest
{
direction = "input";
type = "waitrequest";
width = "1";
Is_Enabled = "1";
}
PORT jtag_debug_trigout
{
width = "1";
direction = "output";
Is_Enabled = "0";
}
PORT jtag_debug_offchip_trace_clk
{
width = "1";
direction = "output";
Is_Enabled = "0";
}
PORT jtag_debug_offchip_trace_data
{
width = "18";
direction = "output";
Is_Enabled = "0";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Is_Instruction_Master = "1";
Has_IRQ = "0";
Irq_Scheme = "individual_requests";
Interrupt_Range = "0-0";
Is_Enabled = "1";
Maximum_Burst_Size = "1";
Burst_On_Burst_Boundaries_Only = "";
Linewrap_Bursts = "";
Interleave_Bursts = "";
Is_Readable = "1";
Is_Writeable = "0";
Address_Group = "0";
}
}
MASTER data_master
{
PORT_WIRING
{
PORT clk
{
direction = "input";
type = "clk";
width = "1";
Is_Enabled = "1";
}
PORT d_address
{
direction = "output";
type = "address";
width = "26";
Is_Enabled = "1";
}
PORT d_byteenable
{
direction = "output";
type = "byteenable";
width = "4";
Is_Enabled = "1";
}
PORT d_irq
{
direction = "input";
type = "irq";
width = "32";
Is_Enabled = "1";
}
PORT d_read
{
direction = "output";
type = "read";
width = "1";
Is_Enabled = "1";
}
PORT d_readdata
{
direction = "input";
type = "readdata";
width = "32";
Is_Enabled = "1";
}
PORT d_waitrequest
{
direction = "input";
type = "waitrequest";
width = "1";
Is_Enabled = "1";
}
PORT d_write
{
direction = "output";
type = "write";
width = "1";
Is_Enabled = "1";
}
PORT d_writedata
{
direction = "output";
type = "writedata";
width = "32";
Is_Enabled = "1";
}
PORT jtag_debug_module_debugaccess_to_roms
{
direction = "output";
type = "debugaccess";
width = "1";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "1";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Is_Data_Master = "1";
Has_IRQ = "1";
Irq_Scheme = "individual_requests";
Interrupt_Range = "0-31";
Is_Enabled = "1";
Maximum_Burst_Size = "1";
Burst_On_Burst_Boundaries_Only = "";
Is_Readable = "1";
Is_Writeable = "1";
Address_Group = "0";
}
}
SLAVE jtag_debug_module
{
PORT_WIRING
{
PORT jtag_debug_module_address
{
direction = "input";
type = "address";
width = "9";
Is_Enabled = "1";
}
PORT jtag_debug_module_begintransfer
{
direction = "input";
type = "begintransfer";
width = "1";
Is_Enabled = "1";
}
PORT jtag_debug_module_clk
{
direction = "input";
type = "clk";
width = "1";
Is_Enabled = "1";
}
PORT jtag_debug_module_debugaccess
{
direction = "input";
type = "debugaccess";
width = "1";
Is_Enabled = "1";
}
PORT jtag_debug_module_readdata
{
direction = "output";
type = "readdata";
width = "32";
Is_Enabled = "1";
}
PORT jtag_debug_module_reset
{
direction = "input";
type = "reset";
width = "1";
Is_Enabled = "1";
}
PORT jtag_debug_module_resetrequest
{
direction = "output";
type = "resetrequest";
width = "1";
Is_Enabled = "1";
}
PORT jtag_debug_module_select
{
direction = "input";
type = "chipselect";
width = "1";
Is_Enabled = "1";
}
PORT jtag_debug_module_write
{
direction = "input";
type = "write";
width = "1";
Is_Enabled = "1";
}
PORT jtag_debug_module_writedata
{
direction = "input";
type = "writedata";
width = "32";
Is_Enabled = "1";
}
PORT reset_n
{
direction = "input";
type = "reset_n";
width = "1";
Is_Enabled = "1";
}
PORT jtag_debug_module_byteenable
{
direction = "input";
type = "byteenable";
width = "4";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Read_Wait_States = "1";
Write_Wait_States = "1";
Register_Incoming_Signals = "1";
Bus_Type = "avalon";
Data_Width = "32";
Address_Width = "9";
Accepts_Internal_Connections = "1";
Requires_Internal_Connections = "instruction_master,data_master";
Accepts_External_Connections = "0";
Is_Enabled = "1";
Address_Alignment = "dynamic";
Base_Address = "0x02120000";
Is_Memory_Device = "1";
Is_Printable_Device = "0";
Uses_Tri_State_Data_Bus = "0";
Has_IRQ = "0";
JTAG_Hub_Base_Id = "1118278";
JTAG_Hub_Instance_Id = "0";
MASTERED_BY cpu/instruction_master
{
priority = "1";
}
MASTERED_BY cpu/data_master
{
priority = "1";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
Is_Readable = "1";
Is_Writeable = "1";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
CPU_Architecture = "nios2";
do_generate = "1";
cpu_selection = "s";
CPU_Implementation = "small";
cache_has_dcache = "0";
cache_has_icache = "1";
cache_dcache_size = "2048";
cache_icache_size = "4096";
include_debug = "0";
include_trace = "0";
include_oci = "1";
debug_level = "2";
oci_offchip_trace = "0";
oci_data_trace = "0";
oci_trace_addr_width = "7";
oci_num_xbrk = "0";
oci_num_dbrk = "0";
oci_dbrk_trace = "0";
oci_dbrk_pairs = "0";
oci_num_pm = "0";
oci_pm_width = "40";
oci_debugreq_signals = "0";
oci_instance_number = "1";
hardware_multiply_present = "1";
hardware_divide_present = "0";
bht_ptr_sz = "8";
reset_slave = "ext_flash/s1";
reset_offset = "0x00000000";
exc_slave = "sdram/s1";
exc_offset = "0x00000020";
break_slave = "cpu/jtag_debug_module";
break_offset = "0x00000020";
altera_internal_test = "0";
full_waveform_signals = "0";
activate_model_checker = "0";
activate_monitors_and_trace = "0";
bit_31_bypass_dcache = "1";
always_bypass_dcache = "0";
always_encrypt = "1";
consistent_synthesis = "0";
ibuf_ptr_sz = "4";
jtb_ptr_sz = "5";
performance_counters_present = "0";
performance_counters_width = "32";
ras_ptr_sz = "4";
inst_decode_in_submodule = "0";
register_dependency_in_submodule = "0";
source_operands_in_submodule = "0";
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