?? std_1s40.ptf
字號:
}
MASTER tightly_coupled_instruction_master_1
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Is_Instruction_Master = "1";
Is_Readable = "1";
Is_Writeable = "0";
Has_IRQ = "0";
Is_Enabled = "0";
Connection_Limit = "1";
Is_Channel = "1";
Address_Group = "0";
}
}
MASTER tightly_coupled_instruction_master_2
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Is_Instruction_Master = "1";
Is_Readable = "1";
Is_Writeable = "0";
Has_IRQ = "0";
Is_Enabled = "0";
Connection_Limit = "1";
Is_Channel = "1";
Address_Group = "0";
}
}
MASTER tightly_coupled_instruction_master_3
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Is_Instruction_Master = "1";
Is_Readable = "1";
Is_Writeable = "0";
Has_IRQ = "0";
Is_Enabled = "0";
Connection_Limit = "1";
Is_Channel = "1";
Address_Group = "0";
}
}
}
MODULE ext_ram_bus
{
class = "altera_avalon_tri_state_bridge";
class_version = "2.0";
SLAVE avalon_slave
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Bridges_To = "tristate_master";
Base_Address = "N/A";
Has_IRQ = "0";
IRQ = "N/A";
Register_Outgoing_Signals = "1";
Register_Incoming_Signals = "1";
MASTERED_BY cpu/instruction_master
{
priority = "1";
}
MASTERED_BY cpu/data_master
{
priority = "1";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
}
}
MASTER tristate_master
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon_tristate";
Bridges_To = "avalon_slave";
}
}
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Is_Bridge = "1";
View
{
MESSAGES
{
}
Is_Collapsed = "1";
}
Clock_Source = "clk";
Top_Level_Ports_Are_Enumerated = "1";
}
}
MODULE ext_flash
{
class = "altera_avalon_cfi_flash";
class_version = "1.1";
iss_model_name = "altera_avalon_flash";
HDL_INFO
{
}
SLAVE s1
{
PORT_WIRING
{
PORT data
{
width = "8";
is_shared = "1";
direction = "inout";
type = "data";
BOARD_COMPONENT altera_nios_dev_board_stratix_1s40
{
component_pin = "U5.31,U5.32,U5.33,U5.34,U5.38,U5.39,U5.40,U5.41";
pin_assignment = "H12,F12,J12,M12,H17,K18,H18,G18";
}
}
PORT address
{
width = "23";
is_shared = "1";
direction = "input";
type = "address";
BOARD_COMPONENT altera_nios_dev_board_stratix_1s40
{
component_pin = "U5.27,U5.22,U5.21,U5.20,U5.19,U5.18,U5.17,U5.16,U5.10,U5.9,U5.42,U5.8,U5.7,U5.6,U5.5,U5.4,U5.3,U5.46,U5.15,U5.43,U5.44,U5.35,U5.2";
pin_assignment = "A4,A3,B3,B5,B4,C4,A5,C5,D5,E6,A6,B7,D6,A7,D7,C6,C7,B6,D8,C8,E8,D9,B9";
}
}
PORT read_n
{
width = "1";
is_shared = "0";
direction = "input";
type = "read_n";
BOARD_COMPONENT altera_nios_dev_board_stratix_1s40
{
component_pin = "U5.30";
pin_assignment = "F19";
}
}
PORT write_n
{
width = "1";
is_shared = "0";
direction = "input";
type = "write_n";
BOARD_COMPONENT altera_nios_dev_board_stratix_1s40
{
component_pin = "U5.11";
pin_assignment = "G19";
}
}
PORT select_n
{
width = "1";
is_shared = "0";
direction = "input";
type = "chipselect_n";
BOARD_COMPONENT altera_nios_dev_board_stratix_1s40
{
component_pin = "U5.28";
pin_assignment = "K19";
}
}
}
WIZARD_SCRIPT_ARGUMENTS
{
class = "altera_avalon_cfi_flash";
flash_reference_designator = "U5";
Supports_Flash_File_System = "1";
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon_tristate";
Is_Memory_Device = "1";
Address_Alignment = "dynamic";
Has_IRQ = "0";
Base_Address = "0x00000000";
Data_Width = "8";
Address_Width = "23";
Write_Wait_States = "160ns";
Read_Wait_States = "160ns";
Setup_Time = "40ns";
Hold_Time = "40ns";
MASTERED_BY ext_ram_bus/tristate_master
{
priority = "1";
}
Is_Base_Locked = "1";
Simulation_Num_Lanes = "1";
Is_Nonvolatile_Storage = "1";
Address_Span = "8388608";
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
Convert_Xs_To_0 = "1";
}
}
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
Instantiate_In_System_Module = "0";
View
{
MESSAGES
{
}
Is_Collapsed = "1";
}
Make_Memory_Model = "1";
Clock_Source = "clk";
Top_Level_Ports_Are_Enumerated = "1";
}
WIZARD_SCRIPT_ARGUMENTS
{
Setup_Value = "40";
Wait_Value = "160";
Hold_Value = "40";
Timing_Units = "ns";
Unit_Multiplier = "1";
Size = "8388608";
MAKE
{
TARGET flashfiles
{
ext_flash
{
Command1 = "@echo Post-processing to create $(notdir $@)";
Dependency = "$(ELF)";
Target_File = "$(EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX)ext_flash.flash";
Command2 = "elf2flash --input=$(ELF) --flash=U5 --boot=$(shell $(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir $(CPU_CLASS))/$(BOOT_COPIER) --outfile=$(EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX)ext_flash.flash --sim_optimize=$(ALT_SIM_OPTIMIZE) --base=0x0 --end=0x7FFFFF --reset=$(CPU_RESET_ADDRESS) ";
}
}
TARGET programflash
{
ext_flash
{
All_Depends_On = "0";
Command1 = "nios2-flash-programmer --input=$(EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX)ext_flash.flash --sof=$(shell $(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir altera_nios_dev_board_stratix_1s40)/system/altera_nios_dev_board_stratix_1s40.sof --device=1 $(JTAG_CABLE) --base=0x00800000 ";
Dependency = "$(EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX)ext_flash.flash";
Target_File = "ext_flash_programflash";
Is_Phony = "1";
}
}
TARGET factory
{
ext_flash
{
All_Depends_On = "0";
Command1 = "sof2flash --flash=U5 --offset=0x600000 --output=factory.flash $(SOF) ";
Command2 = "nios2-flash-programmer --input=factory.flash --sof=$(shell $(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir altera_nios_dev_board_stratix_1s40)/system/altera_nios_dev_board_stratix_1s40.sof --device=1 $(JTAG_CABLE) --base=0x00800000 ";
Dependency = "";
Is_Phony = "1";
Target_File = "ext_flash_factory_configuration";
}
}
MACRO
{
EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX = "$(EXT_FLASH_FLASHTARGET_TMP1:0=)";
EXT_FLASH_FLASHTARGET_TMP1 = "$(ALT_SIM_OPTIMIZE:1=RUN_ON_HDL_SIMULATOR_ONLY_)";
}
MASTER cpu
{
MACRO
{
BOOT_COPIER = "boot_loader_cfi.srec";
CPU_CLASS = "altera_nios2";
CPU_RESET_ADDRESS = "0x0";
}
}
TARGET delete_placeholder_warning
{
ext_flash
{
Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
Is_Phony = "1";
Target_File = "do_delete_placeholder_warning";
}
}
TARGET sim
{
ext_flash
{
Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";
Command3 = "touch $(SIMDIR)/dummy_file";
Dependency = "$(ELF)";
Target_File = "$(SIMDIR)/dummy_file";
}
}
TARGET user
{
ext_flash
{
All_Depends_On = "0";
Command1 = "sof2flash --flash=U5 --offset=0x400000 --output=user.flash $(SOF) ";
Command2 = "nios2-flash-programmer --input=user.flash --sof=$(shell $(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir altera_nios_dev_board_stratix_1s40)/system/altera_nios_dev_board_stratix_1s40.sof --device=1 $(JTAG_CABLE) --base=0x00800000 ";
Dependency = "";
Is_Phony = "1";
Target_File = "ext_flash_user_configuration";
}
}
TARGET programflashnoelfdependency
{
ext_flash
{
All_Depends_On = "0";
Command1 = "nios2-flash-programmer --input=$(EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX)ext_flash.flash --sof=$(shell $(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir altera_nios_dev_board_stratix_1s40)/system/altera_nios_dev_board_stratix_1s40.sof --device=1 $(JTAG_CABLE) --base=0x00800000 ";
Is_Phony = "1";
Target_File = "ext_flash_programflashnoelf";
}
}
}
contents_info = "";
}
}
MODULE ext_ram
{
class = "altera_nios_dev_kit_stratix_edition_sram2";
class_version = "1.0";
iss_model_name = "altera_memory";
HDL_INFO
{
}
WIZARD_SCRIPT_ARGUMENTS
{
sram_memory_size = "1024";
sram_memory_units = "1024";
sram_data_width = "32";
MAKE
{
TARGET delete_placeholder_warning
{
ext_ram
{
Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
Is_Phony = "1";
Target_File = "do_delete_placeholder_warning";
}
}
TARGET sim
{
ext_ram
{
Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";
Command3 = "touch $(SIMDIR)/dummy_file";
Dependency = "$(ELF)";
Target_File = "$(SIMDIR)/dummy_file";
}
}
}
contents_info = "";
}
SLAVE s1
{
PORT_WIRING
{
PORT data
{
width = "32";
is_shared = "1";
direction = "inout";
type = "data";
BOARD_COMPONENT altera_nios_dev_board_stratix_1s40
{
component_pin = "U35.7,U35.8,U35.9,U35.10,U35.13,U35.14,U35.15,U35.16,U35.29,U35.30,U35.31,U35.32,U35.35,U35.36,U35.37,U35.38,U36.7,U36.8,U36.9,U36.10,U36.13,U36.14,U36.15,U36.16,U36.29,U36.30,U36.31,U36.32,U36.35,U36.36,U36.37,U36.38";
pin_assignment = "H12,F12,J12,M12,H17,K18,H18,G18,B8,A8,A9,C9,E10,A10,C10,B10,A11,C11,D11,B11,D10,G10,F10,H11,G11,F8,J9,J13,L13,M11,L11,G7";
}
}
PORT address
{
width = "18";
is_shared = "1";
direction = "input";
type = "address";
lsb = "2";
BOARD_COMPONENT altera_nios_dev_board_stratix_1s40
{
component_pin = "U35.1,U35.2,U35.3,U35.4,U35.5,U35.18,U35.19,U35.20,U35.21,U35.22,U35.23,U35.24,U35.25,U35.26,U35.27,U35.42,U35.43,U35.44";
pin_assignment = "B3,B5,B4,C4,A5,C5,D5,E6,A6,B7,D6,A7,D7,C6,C7,B6,D8,C8";
}
}
PORT read_n
{
width = "1";
is_shared = "0";
direction = "input";
type = "read_n";
BOARD_COMPONENT altera_nios_dev_board_stratix_1s40
{
component_pin = "U35.41";
pin_assignment = "B26";
}
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