cpu_data_master_read,
                            cpu_data_master_write,
                            cpu_data_master_writedata,
                            reset_n,

                           // outputs:
                            cf_ide_address,
                            cf_ide_chipselect_n,
                            cf_ide_irq_from_sa,
                            cf_ide_read_n,
                            cf_ide_readdata_from_sa,
                            cf_ide_reset_n,
                            cf_ide_wait_counter_eq_0,
                            cf_ide_wait_counter_eq_1,
                            cf_ide_write_n,
                            cf_ide_writedata,
                            cpu_data_master_granted_cf_ide,
                            cpu_data_master_qualified_request_cf_ide,
                            cpu_data_master_read_data_valid_cf_ide,
                            cpu_data_master_requests_cf_ide,
                            d1_cf_ide_end_xfer
                         );

  output  [  3: 0] cf_ide_address;
  output           cf_ide_chipselect_n;
  output           cf_ide_irq_from_sa;
  output           cf_ide_read_n;
  output  [ 15: 0] cf_ide_readdata_from_sa;
  output           cf_ide_reset_n;
  output           cf_ide_wait_counter_eq_0;
  output           cf_ide_wait_counter_eq_1;
  output           cf_ide_write_n;
  output  [ 15: 0] cf_ide_writedata;
  output           cpu_data_master_granted_cf_ide;
  output           cpu_data_master_qualified_request_cf_ide;
  output           cpu_data_master_read_data_valid_cf_ide;
  output           cpu_data_master_requests_cf_ide;
  output           d1_cf_ide_end_xfer;
  input            cf_ide_irq;
  input   [ 15: 0] cf_ide_readdata;
  input            clk;
  input   [ 25: 0] cpu_data_master_address_to_slave;
  input            cpu_data_master_read;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input            reset_n;

  wire    [  3: 0] cf_ide_address;
  wire             cf_ide_allgrants;
  wire             cf_ide_allow_new_arb_cycle;
  wire             cf_ide_any_continuerequest;
  wire             cf_ide_arb_counter_enable;
  reg     [  2: 0] cf_ide_arb_share_counter;
  wire    [  2: 0] cf_ide_arb_share_counter_next_value;
  wire    [  2: 0] cf_ide_arb_share_set_values;
  wire             cf_ide_arbitration_holdoff_internal;
  wire             cf_ide_beginbursttransfer_internal;
  wire             cf_ide_begins_xfer;
  wire             cf_ide_chipselect_n;
  wire    [  4: 0] cf_ide_counter_load_value;
  wire             cf_ide_end_xfer;
  wire             cf_ide_firsttransfer;
  wire             cf_ide_grant_vector;
  wire             cf_ide_in_a_read_cycle;
  wire             cf_ide_in_a_write_cycle;
  wire             cf_ide_irq_from_sa;
  wire             cf_ide_master_qreq_vector;
  wire             cf_ide_read_n;
  wire    [ 15: 0] cf_ide_readdata_from_sa;
  wire             cf_ide_reset_n;
  reg              cf_ide_slavearbiterlockenable;
  reg     [  4: 0] cf_ide_wait_counter;
  wire             cf_ide_wait_counter_eq_0;
  wire             cf_ide_wait_counter_eq_1;
  wire             cf_ide_waits_for_read;
  wire             cf_ide_waits_for_write;
  wire             cf_ide_write_n;
  wire    [ 15: 0] cf_ide_writedata;
  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_cf_ide;
  wire             cpu_data_master_qualified_request_cf_ide;
  wire             cpu_data_master_read_data_valid_cf_ide;
  wire             cpu_data_master_requests_cf_ide;
  wire             cpu_data_master_saved_grant_cf_ide;
  reg              d1_cf_ide_end_xfer;
  reg              d1_reasons_to_wait;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             wait_for_cf_ide_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~cf_ide_end_xfer;
    end


  assign cf_ide_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_cf_ide));
  assign cpu_data_master_requests_cf_ide = ({cpu_data_master_address_to_slave[25 : 6] , 6'b0} == 26'h800000) & (cpu_data_master_read | cpu_data_master_write);
  //assign cf_ide_readdata_from_sa = cf_ide_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign cf_ide_readdata_from_sa = cf_ide_readdata;

  //cf_ide_arb_share_counter set values, which is an e_mux
  assign cf_ide_arb_share_set_values = 1;

  //cf_ide_arb_share_counter_next_value assignment, which is an e_assign
  assign cf_ide_arb_share_counter_next_value = cf_ide_firsttransfer ? (cf_ide_arb_share_set_values - 1) : |cf_ide_arb_share_counter ? (cf_ide_arb_share_counter - 1) : 0;

  //cf_ide_allgrants all slave grants, which is an e_mux
  assign cf_ide_allgrants = |cf_ide_grant_vector;

  //cf_ide_end_xfer assignment, which is an e_assign
  assign cf_ide_end_xfer = ~(cf_ide_waits_for_read | cf_ide_waits_for_write);

  //cf_ide_arb_share_counter arbitration counter enable, which is an e_assign
  assign cf_ide_arb_counter_enable = cf_ide_end_xfer & cf_ide_allgrants;

  //cf_ide_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cf_ide_arb_share_counter <= 0;
      else if (cf_ide_arb_counter_enable)
          cf_ide_arb_share_counter <= cf_ide_arb_share_counter_next_value;
    end


  //cf_ide_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cf_ide_slavearbiterlockenable <= 0;
      else if (|cf_ide_master_qreq_vector & cf_ide_end_xfer)
          cf_ide_slavearbiterlockenable <= |cf_ide_arb_share_counter_next_value;
    end


  //cpu/data_master cf/ide arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = cf_ide_slavearbiterlockenable & cpu_data_master_continuerequest;

  //cf_ide_any_continuerequest at least one master continues requesting, which is an e_assign
  assign cf_ide_any_continuerequest = 0;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 0;

  assign cpu_data_master_qualified_request_cf_ide = cpu_data_master_requests_cf_ide;
  //cf_ide_writedata mux, which is an e_mux
  assign cf_ide_writedata = cpu_data_master_writedata;

  //master is always granted when requested
  assign cpu_data_master_granted_cf_ide = cpu_data_master_qualified_request_cf_ide;

  //cpu/data_master saved-grant cf/ide, which is an e_assign
  assign cpu_data_master_saved_grant_cf_ide = cpu_data_master_requests_cf_ide;

  //allow new arb cycle for cf/ide, which is an e_assign
  assign cf_ide_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign cf_ide_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign cf_ide_master_qreq_vector = 1;

  //cf_ide_reset_n assignment, which is an e_assign
  assign cf_ide_reset_n = reset_n;

  assign cf_ide_chipselect_n = ~cpu_data_master_granted_cf_ide;
  //cf_ide_firsttransfer first transaction, which is an e_assign
  assign cf_ide_firsttransfer = ~(cf_ide_slavearbiterlockenable & cf_ide_any_continuerequest);

  //cf_ide_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign cf_ide_beginbursttransfer_internal = cf_ide_begins_xfer & cf_ide_firsttransfer;

  //cf_ide_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
  assign cf_ide_arbitration_holdoff_internal = cf_ide_begins_xfer & cf_ide_firsttransfer;

  //~cf_ide_read_n assignment, which is an e_mux
  assign cf_ide_read_n = ~(((cpu_data_master_granted_cf_ide & cpu_data_master_read))& ~cf_ide_begins_xfer & (cf_ide_wait_counter < 27));

  //~cf_ide_write_n assignment, which is an e_mux
  assign cf_ide_write_n = ~(((cpu_data_master_granted_cf_ide & cpu_data_master_write)) & ~cf_ide_begins_xfer & (cf_ide_wait_counter >= 2) & (cf_ide_wait_counter < 27));

  //cf_ide_address mux, which is an e_mux
  assign cf_ide_address = cpu_data_master_address_to_slave >> 2;

  //d1_cf_ide_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_cf_ide_end_xfer <= 1;
      else if (1)
          d1_cf_ide_end_xfer <= cf_ide_end_xfer;
    end


  //cf_ide_wait_counter_eq_1 assignment, which is an e_assign
  assign cf_ide_wait_counter_eq_1 = cf_ide_wait_counter == 1;

  //cf_ide_waits_for_read in a cycle, which is an e_mux
  assign cf_ide_waits_for_read = cf_ide_in_a_read_cycle & wait_for_cf_ide_counter;

  //cf_ide_in_a_read_cycle assignment, which is an e_assign
  assign cf_ide_in_a_read_cycle = cpu_data_master_granted_cf_ide & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = cf_ide_in_a_read_cycle;

  //cf_ide_waits_for_write in a cycle, which is an e_mux
  assign cf_ide_waits_for_write = cf_ide_in_a_write_cycle & wait_for_cf_ide_counter;

  //cf_ide_in_a_write_cycle assignment, which is an e_assign
  assign cf_ide_in_a_write_cycle = cpu_data_master_granted_cf_ide & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = cf_ide_in_a_write_cycle;

  assign cf_ide_wait_counter_eq_0 = cf_ide_wait_counter == 0;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cf_ide_wait_counter <= 0;
      else if (1)
          cf_ide_wait_counter <= cf_ide_counter_load_value;
    end


  assign cf_ide_counter_load_value = ((cf_ide_in_a_read_cycle & cf_ide_begins_xfer))? 29 :
    ((cf_ide_in_a_write_cycle & cf_ide_begins_xfer))? 29 :
    (~cf_ide_wait_counter_eq_0)? cf_ide_wait_counter - 1 :
    0;

  assign wait_for_cf_ide_counter = cf_ide_begins_xfer | ~cf_ide_wait_counter_eq_0;
  //assign cf_ide_irq_from_sa = cf_ide_irq so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign cf_ide_irq_from_sa = cf_ide_irq;


  // synthesis attribute cf_ide_arbitrator auto_dissolve FALSE

endmodule


module cpu_jtag_debug_module_arbitrator (
                                          // inputs:
                                           clk,
                                           cpu_data_master_address_to_slave,