?? cpu_test_bench.v
字號:
module cpu_test_bench (
// inputs:
E_src1,
E_src2,
E_valid,
M_alu_result,
M_bstatus_reg,
M_cmp_result,
M_ctrl_ld_non_io,
M_dst_regnum,
M_en,
M_estatus_reg,
M_ienable_reg,
M_ipending_reg,
M_iw,
M_mem_byte_en,
M_op_hbreak,
M_op_intr,
M_pcb,
M_st_data,
M_status_reg,
M_valid,
M_wr_data_unfiltered,
M_wr_dst_reg,
W_dst_regnum,
W_iw,
W_iw_op,
W_iw_opx,
W_pcb,
W_valid,
W_wr_data,
W_wr_dst_reg,
clk,
d_address,
d_byteenable,
d_read,
d_write,
i_address,
i_read,
i_readdatavalid,
reset_n,
// outputs:
E_src1_eq_src2,
M_wr_data_filtered
);
output E_src1_eq_src2;
output [ 31: 0] M_wr_data_filtered;
input [ 31: 0] E_src1;
input [ 31: 0] E_src2;
input E_valid;
input [ 31: 0] M_alu_result;
input M_bstatus_reg;
input M_cmp_result;
input M_ctrl_ld_non_io;
input [ 4: 0] M_dst_regnum;
input M_en;
input M_estatus_reg;
input [ 31: 0] M_ienable_reg;
input [ 31: 0] M_ipending_reg;
input [ 31: 0] M_iw;
input [ 3: 0] M_mem_byte_en;
input M_op_hbreak;
input M_op_intr;
input [ 25: 0] M_pcb;
input [ 31: 0] M_st_data;
input M_status_reg;
input M_valid;
input [ 31: 0] M_wr_data_unfiltered;
input M_wr_dst_reg;
input [ 4: 0] W_dst_regnum;
input [ 31: 0] W_iw;
input [ 5: 0] W_iw_op;
input [ 5: 0] W_iw_opx;
input [ 25: 0] W_pcb;
input W_valid;
input [ 31: 0] W_wr_data;
input W_wr_dst_reg;
input clk;
input [ 25: 0] d_address;
input [ 3: 0] d_byteenable;
input d_read;
input d_write;
input [ 25: 0] i_address;
input i_read;
input i_readdatavalid;
input reset_n;
wire E_src1_eq_src2;
wire [ 32: 0] E_src1_src2_fast_cmp;
reg [ 25: 0] M_target_pcb;
wire [ 31: 0] M_wr_data_filtered;
wire M_wr_data_unfiltered_0_is_x;
wire M_wr_data_unfiltered_10_is_x;
wire M_wr_data_unfiltered_11_is_x;
wire M_wr_data_unfiltered_12_is_x;
wire M_wr_data_unfiltered_13_is_x;
wire M_wr_data_unfiltered_14_is_x;
wire M_wr_data_unfiltered_15_is_x;
wire M_wr_data_unfiltered_16_is_x;
wire M_wr_data_unfiltered_17_is_x;
wire M_wr_data_unfiltered_18_is_x;
wire M_wr_data_unfiltered_19_is_x;
wire M_wr_data_unfiltered_1_is_x;
wire M_wr_data_unfiltered_20_is_x;
wire M_wr_data_unfiltered_21_is_x;
wire M_wr_data_unfiltered_22_is_x;
wire M_wr_data_unfiltered_23_is_x;
wire M_wr_data_unfiltered_24_is_x;
wire M_wr_data_unfiltered_25_is_x;
wire M_wr_data_unfiltered_26_is_x;
wire M_wr_data_unfiltered_27_is_x;
wire M_wr_data_unfiltered_28_is_x;
wire M_wr_data_unfiltered_29_is_x;
wire M_wr_data_unfiltered_2_is_x;
wire M_wr_data_unfiltered_30_is_x;
wire M_wr_data_unfiltered_31_is_x;
wire M_wr_data_unfiltered_3_is_x;
wire M_wr_data_unfiltered_4_is_x;
wire M_wr_data_unfiltered_5_is_x;
wire M_wr_data_unfiltered_6_is_x;
wire M_wr_data_unfiltered_7_is_x;
wire M_wr_data_unfiltered_8_is_x;
wire M_wr_data_unfiltered_9_is_x;
wire [ 55: 0] W_inst;
wire W_op_add;
wire W_op_addi;
wire W_op_and;
wire W_op_andhi;
wire W_op_andi;
wire W_op_beq;
wire W_op_bge;
wire W_op_bgeu;
wire W_op_blt;
wire W_op_bltu;
wire W_op_bne;
wire W_op_br;
wire W_op_break;
wire W_op_bret;
wire W_op_call;
wire W_op_callr;
wire W_op_cmpeq;
wire W_op_cmpeqi;
wire W_op_cmpge;
wire W_op_cmpgei;
wire W_op_cmpgeu;
wire W_op_cmpgeui;
wire W_op_cmplt;
wire W_op_cmplti;
wire W_op_cmpltu;
wire W_op_cmpltui;
wire W_op_cmpne;
wire W_op_cmpnei;
wire W_op_custom;
wire W_op_div;
wire W_op_divu;
wire W_op_eret;
wire W_op_flushd;
wire W_op_flushda;
wire W_op_flushi;
wire W_op_flushp;
wire W_op_hbreak;
wire W_op_initd;
wire W_op_initi;
wire W_op_intr;
wire W_op_jmp;
wire W_op_ldb;
wire W_op_ldbio;
wire W_op_ldbu;
wire W_op_ldbuio;
wire W_op_ldh;
wire W_op_ldhio;
wire W_op_ldhu;
wire W_op_ldhuio;
wire W_op_ldw;
wire W_op_ldwio;
wire W_op_mul;
wire W_op_muli;
wire W_op_mulxss;
wire W_op_mulxsu;
wire W_op_mulxuu;
wire W_op_nextpc;
wire W_op_nor;
wire W_op_opx;
wire W_op_or;
wire W_op_orhi;
wire W_op_ori;
wire W_op_rdctl;
wire W_op_ret;
wire W_op_rol;
wire W_op_roli;
wire W_op_ror;
wire W_op_rsv01;
wire W_op_rsv02;
wire W_op_rsv09;
wire W_op_rsv10;
wire W_op_rsv17;
wire W_op_rsv18;
wire W_op_rsv19;
wire W_op_rsv25;
wire W_op_rsv26;
wire W_op_rsv29;
wire W_op_rsv31;
wire W_op_rsv33;
wire W_op_rsv34;
wire W_op_rsv41;
wire W_op_rsv42;
wire W_op_rsv49;
wire W_op_rsv56;
wire W_op_rsv57;
wire W_op_rsv61;
wire W_op_rsv62;
wire W_op_rsv63;
wire W_op_rsvx00;
wire W_op_rsvx10;
wire W_op_rsvx15;
wire W_op_rsvx17;
wire W_op_rsvx20;
wire W_op_rsvx21;
wire W_op_rsvx25;
wire W_op_rsvx33;
wire W_op_rsvx34;
wire W_op_rsvx35;
wire W_op_rsvx42;
wire W_op_rsvx43;
wire W_op_rsvx44;
wire W_op_rsvx47;
wire W_op_rsvx50;
wire W_op_rsvx51;
wire W_op_rsvx55;
wire W_op_rsvx56;
wire W_op_rsvx60;
wire W_op_rsvx62;
wire W_op_rsvx63;
wire W_op_sll;
wire W_op_slli;
wire W_op_sra;
wire W_op_srai;
wire W_op_srl;
wire W_op_srli;
wire W_op_stb;
wire W_op_stbio;
wire W_op_sth;
wire W_op_sthio;
wire W_op_stw;
wire W_op_stwio;
wire W_op_sub;
wire W_op_sync;
wire W_op_trap;
wire W_op_wrctl;
wire W_op_xor;
wire W_op_xorhi;
wire W_op_xori;
wire [ 55: 0] W_vinst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
M_target_pcb <= 0;
else if (M_en)
M_target_pcb <= E_src1[25 : 0];
end
assign E_src1_src2_fast_cmp = {1'b0, E_src1 ^ E_src2} - 33'b1;
assign E_src1_eq_src2 = E_src1_src2_fast_cmp[32];
assign W_op_muli = W_iw_op[5 : 0] == 36;
assign W_op_bge = W_iw_op[5 : 0] == 14;
assign W_op_ldbio = W_iw_op[5 : 0] == 39;
assign W_op_cmpnei = W_iw_op[5 : 0] == 24;
assign W_op_ori = W_iw_op[5 : 0] == 20;
assign W_op_stwio = W_iw_op[5 : 0] == 53;
assign W_op_rsv01 = W_iw_op[5 : 0] == 1;
assign W_op_rsv02 = W_iw_op[5 : 0] == 2;
assign W_op_cmpltui = W_iw_op[5 : 0] == 48;
assign W_op_bgeu = W_iw_op[5 : 0] == 46;
assign W_op_beq = W_iw_op[5 : 0] == 38;
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