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//agreement for further details.

// synthesis translate_off
`timescale 1ns / 100ps
// synthesis translate_on
//------------------------------------------------------------------------------
//This confidential and proprietary software may be used only as authorized by
//a licensing agreement from Altera Corporation.
//(C) COPYRIGHT 2004 ALTERA CORPORATION
//ALL RIGHTS RESERVED
//The entire notice above must be reproduced on all authorized copies and any
//such reproduction must be pursuant to a licensing agreement from Altera.
//Title        : Memory Controller Example Driver
//Project      : DDR SDRAM Controller
//File         : ddr_sdram_example_driver
//Revision     : V3.2.0
//Abstract:
//Configurable memory controller driver example.
//Configurable memory parameters
//- Data Width
//- Burst Length
//- Address Size (Chipsels, Bankbits, Colbits, Rowbits)
//Configure test setup
//- mode (write all, read all) or (write one, read one)
//- start address / stop address
//- address increment size (options)
//Pass Fail
//- Per byte lane (non-persistent)
//- complete (persistent)										
//----------------------------------------------------------------------------------
//Parameters:
//local Interface Data Width         : 32
//DQ_PER_DQS                         : 8
//LOCAL_AVALON_IF                    : true
//MEM_CHIPSELS                       : 1
//MEM_CHIP_BITS                      : 0
//MEM_BANK_BITS                      : 2
//MEM_ROW_BITS                       : 13
//MEM_COL_BITS                       : 9
//LOCAL_BURST_LEN                    : 1
//LOCAL_BURST_LEN_BITS               : 1
//----------------------------------------------------------------------------------
//FSM States
//S_IDLE				   : 0
//S_WRITE_ALL                        : 1
//S_WRITE_ALL_WAIT		   : 2
//S_READ_ALL                         : 3
//S_READ_ALL_WAIT                    : 4
//S_WRITE                            : 5
//S_WRITE_WAIT                       : 6
//S_READ                             : 7
//S_READ_WAIT                        : 8
//S_BURST_WRITE_ALL                  : 10
//S_BURST_READ_ALL                   : 11
//S_BURST_WRITE_WAIT                 : 12
//S_BURST_READ_WAIT                  : 13
//S_INIT                             : 9
//----------------------------------------------------------------------------------

module ddr_sdram_example_driver (
                                  // inputs:
                                   clk,
                                   local_rdata,
                                   local_rdata_valid,
                                   local_ready,
                                   reset_n,

                                  // outputs:
                                   burst_begin,
                                   local_bank_addr,
                                   local_be,
                                   local_col_addr,
                                   local_cs_addr,
                                   local_read_req,
                                   local_row_addr,
                                   local_size,
                                   local_wdata,
                                   local_write_req,
                                   pnf_per_byte,
                                   pnf_persist,
                                   test_complete
                                );

  parameter MEM_BANK_BITS = 2;
  parameter MEM_COL_BITS = 9;
  parameter col_addr_max = 511;
  parameter LOCAL_BURST_LEN_BITS = 1;
  parameter LOCAL_BURST_LEN = 1;
  parameter LOCAL_ADDR_BITS = 24;
  parameter MEM_CHIPSELS = 1;
  parameter cs_addr_max = 1;
  parameter LOCAL_DATA_BITS = 32;
  parameter row_addr_max = 8191;
  parameter bank_addr_max = 3;
  parameter MEM_ROW_BITS = 13;
  parameter MEM_DQ_PER_DQS = 8;
  parameter WRITE_ALL_MODE = 1;
  parameter AVALON_IF = "true";
  parameter MEM_CHIP_BITS = 0;


  output           burst_begin;
  output  [  1: 0] local_bank_addr;
  output  [  3: 0] local_be;
  output  [  8: 0] local_col_addr;
  output           local_cs_addr;
  output           local_read_req;
  output  [ 12: 0] local_row_addr;
  output           local_size;
  output  [ 31: 0] local_wdata;
  output           local_write_req;
  output  [  3: 0] pnf_per_byte;
  output           pnf_persist;
  output           test_complete;
  input            clk;
  input   [ 31: 0] local_rdata;
  input            local_rdata_valid;
  input            local_ready;
  input            reset_n;

  wire             LOCAL_BURST_LEN_s;
  wire    [  1: 0] MAX_BANK;
  wire             MAX_CHIPSEL;
  wire    [  8: 0] MAX_COL;
  wire    [ 12: 0] MAX_ROW;
  wire             MIN_CHIPSEL;
  wire             avalon_burst_mode;
  wire             avalon_read_burst_max_address;
  reg     [  1: 0] bank_addr;
  wire    [  3: 0] be;
  reg     [  2: 0] burst_beat_count;
  reg              burst_begin;
  reg     [  8: 0] col_addr;
  wire    [  3: 0] compare;
  reg     [  3: 0] compare_reg;
  reg     [  3: 0] compare_valid;
  reg     [  3: 0] compare_valid_reg;
  reg              cs_addr;
  wire    [ 31: 0] dgen_data;
  reg              dgen_enable;
  reg     [ 31: 0] dgen_ldata;
  reg              dgen_load;
  wire             dgen_pause;
  reg              last_rdata_valid;
  reg              last_wdata_req;
  wire    [  1: 0] local_bank_addr;
  wire    [  3: 0] local_be;
  wire    [  8: 0] local_col_addr;
  wire             local_cs_addr;
  wire             local_read_req;
  wire    [ 12: 0] local_row_addr;
  wire             local_size;
  wire    [ 31: 0] local_wdata;
  wire             local_write_req;
  wire    [  3: 0] pnf_per_byte;
  reg              pnf_persist;
  reg              pnf_persist1;
  wire             reached_max_address;
  reg              reached_max_count;
  reg              read_req;
  reg     [  7: 0] reads_remaining;
  reg              reset_address;
  reg     [ 12: 0] row_addr;
  wire             size;
  reg     [  3: 0] state;
  reg              test_complete;
  reg              wait_first_write_data;
  wire    [ 31: 0] wdata;
  wire             wdata_req;
  reg              write_req;
  reg     [  7: 0] writes_remaining;
  assign avalon_burst_mode = 0;
  assign MIN_CHIPSEL = 0;
  assign MAX_CHIPSEL = 0;
  assign MAX_ROW = 3;
  assign MAX_BANK = 3;
  assign MAX_COL = 16;
  //


  assign local_cs_addr = cs_addr;

  assign local_row_addr = row_addr;
  assign local_bank_addr = bank_addr;
  assign local_col_addr = col_addr;
  assign local_write_req = write_req;
  assign local_read_req = read_req;
  assign local_wdata = wdata;
  assign wdata = dgen_data;
  //The LOCAL_BURST_LEN_s is a signal used insted of the parameter LOCAL_BURST_LEN
  assign LOCAL_BURST_LEN_s = 1;
  //LOCAL INTERFACE (AVALON)
  assign wdata_req = write_req && local_ready;

  // Generate new data (enable lfsr) when writing or reading valid data
  assign dgen_pause = ~ (wdata_req | local_rdata_valid);

  //


  assign local_be = be;

  assign be = -1;
  assign pnf_per_byte = compare_valid_reg;
  assign local_size = size;
  //FIX
  assign size = LOCAL_BURST_LEN_s;

  assign reached_max_address = (col_addr >= (MAX_COL - (1 * 2))) && (row_addr == MAX_ROW) && (bank_addr == MAX_BANK) && (cs_addr == MAX_CHIPSEL);
  assign avalon_read_burst_max_address = (col_addr >= (MAX_COL - (1 * 4))) && (row_addr == MAX_ROW) && (bank_addr == MAX_BANK) && (cs_addr == MAX_CHIPSEL);
  example_lfsr8 LFSRGEN_0_lfsr_inst
    (
      .clk (clk),
      .data (dgen_data[7 : 0]),
      .enable (dgen_enable),
      .ldata (dgen_ldata[7 : 0]),
      .load (dgen_load),
      .pause (dgen_pause),
      .reset_n (reset_n)
    );

  defparam LFSRGEN_0_lfsr_inst.seed = 1;

  // 8 bit comparator per local byte lane
  assign compare[0] = dgen_data[7 : 0] == local_rdata[7 : 0];

  example_lfsr8 LFSRGEN_1_lfsr_inst
    (
      .clk (clk),
      .data (dgen_data[15 : 8]),
      .enable (dgen_enable),
      .ldata (dgen_ldata[15 : 8]),
      .load (dgen_load),
      .pause (dgen_pause),
      .reset_n (reset_n)
    );

  defparam LFSRGEN_1_lfsr_inst.seed = 11;

  // 8 bit comparator per local byte lane
  assign compare[1] = dgen_data[15 : 8] == local_rdata[15 : 8];

  example_lfsr8 LFSRGEN_2_lfsr_inst
    (
      .clk (clk),
      .data (dgen_data[23 : 16]),
      .enable (dgen_enable),
      .ldata (dgen_ldata[23 : 16]),
      .load (dgen_load),
      .pause (dgen_pause),
      .reset_n (reset_n)
    );

  defparam LFSRGEN_2_lfsr_inst.seed = 21;

  // 8 bit comparator per local byte lane
  assign compare[2] = dgen_data[23 : 16] == local_rdata[23 : 16];

  example_lfsr8 LFSRGEN_3_lfsr_inst
    (
      .clk (clk),
      .data (dgen_data[31 : 24]),
      .enable (dgen_enable),
      .ldata (dgen_ldata[31 : 24]),
      .load (dgen_load),
      .pause (dgen_pause),
      .reset_n (reset_n)
    );

  defparam LFSRGEN_3_lfsr_inst.seed = 31;

  // 8 bit comparator per local byte lane
  assign compare[3] = dgen_data[31 : 24] == local_rdata[31 : 24];

  //
  //-----------------------------------------------------------------
  //Main clocked process
  //-----------------------------------------------------------------
  //Read / Write control state machine & address counter
  //-----------------------------------------------------------------
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
        begin
          //Reset - asynchronously force all register outputs LOW
          state <= 1'b0;

          write_req <= 1'b0;
          read_req <= 1'b0;
          burst_begin <= 0;
          burst_beat_count <= 0;
          cs_addr <= 0;
          row_addr <= 0;
          bank_addr <= 0;
          col_addr <= 0;
          dgen_enable <= 1'b0;
          dgen_load <= 1'b0;
          wait_first_write_data <= 1'b0;
          reached_max_count <= 1'b0;
          test_complete <= 1'b0;
          writes_remaining <= 0;
          reads_remaining <= 0;
          reset_address <= 1'b0;
        end
      else 
        begin
          reset_address <= 1'b0;
          reached_max_count <= reached_max_address;
          read_req <= 1'b0;
          write_req <= 1'b0;
          dgen_load <= 1'b0;
          test_complete <= 1'b0;
          if (last_wdata_req)
              wait_first_write_data <= 0;
          if (write_req && local_ready)