?? std_2c35.v
字號:
cpu_data_master_byteenable,
cpu_data_master_debugaccess,
cpu_data_master_read,
cpu_data_master_write,
cpu_data_master_writedata,
cpu_instruction_master_address_to_slave,
cpu_instruction_master_latency_counter,
cpu_instruction_master_read,
cpu_instruction_master_read_data_valid_ddr_sdram_s1_shift_register,
cpu_jtag_debug_module_readdata,
cpu_jtag_debug_module_resetrequest,
reset_n,
// outputs:
cpu_data_master_granted_cpu_jtag_debug_module,
cpu_data_master_qualified_request_cpu_jtag_debug_module,
cpu_data_master_read_data_valid_cpu_jtag_debug_module,
cpu_data_master_requests_cpu_jtag_debug_module,
cpu_instruction_master_granted_cpu_jtag_debug_module,
cpu_instruction_master_qualified_request_cpu_jtag_debug_module,
cpu_instruction_master_read_data_valid_cpu_jtag_debug_module,
cpu_instruction_master_requests_cpu_jtag_debug_module,
cpu_jtag_debug_module_address,
cpu_jtag_debug_module_begintransfer,
cpu_jtag_debug_module_byteenable,
cpu_jtag_debug_module_chipselect,
cpu_jtag_debug_module_debugaccess,
cpu_jtag_debug_module_readdata_from_sa,
cpu_jtag_debug_module_reset,
cpu_jtag_debug_module_reset_n,
cpu_jtag_debug_module_resetrequest_from_sa,
cpu_jtag_debug_module_write,
cpu_jtag_debug_module_writedata,
d1_cpu_jtag_debug_module_end_xfer
);
output cpu_data_master_granted_cpu_jtag_debug_module;
output cpu_data_master_qualified_request_cpu_jtag_debug_module;
output cpu_data_master_read_data_valid_cpu_jtag_debug_module;
output cpu_data_master_requests_cpu_jtag_debug_module;
output cpu_instruction_master_granted_cpu_jtag_debug_module;
output cpu_instruction_master_qualified_request_cpu_jtag_debug_module;
output cpu_instruction_master_read_data_valid_cpu_jtag_debug_module;
output cpu_instruction_master_requests_cpu_jtag_debug_module;
output [ 8: 0] cpu_jtag_debug_module_address;
output cpu_jtag_debug_module_begintransfer;
output [ 3: 0] cpu_jtag_debug_module_byteenable;
output cpu_jtag_debug_module_chipselect;
output cpu_jtag_debug_module_debugaccess;
output [ 31: 0] cpu_jtag_debug_module_readdata_from_sa;
output cpu_jtag_debug_module_reset;
output cpu_jtag_debug_module_reset_n;
output cpu_jtag_debug_module_resetrequest_from_sa;
output cpu_jtag_debug_module_write;
output [ 31: 0] cpu_jtag_debug_module_writedata;
output d1_cpu_jtag_debug_module_end_xfer;
input clk;
input [ 26: 0] cpu_data_master_address_to_slave;
input [ 3: 0] cpu_data_master_byteenable;
input cpu_data_master_debugaccess;
input cpu_data_master_read;
input cpu_data_master_write;
input [ 31: 0] cpu_data_master_writedata;
input [ 26: 0] cpu_instruction_master_address_to_slave;
input [ 2: 0] cpu_instruction_master_latency_counter;
input cpu_instruction_master_read;
input [ 15: 0] cpu_instruction_master_read_data_valid_ddr_sdram_s1_shift_register;
input [ 31: 0] cpu_jtag_debug_module_readdata;
input cpu_jtag_debug_module_resetrequest;
input reset_n;
wire cpu_data_master_arbiterlock;
wire cpu_data_master_continuerequest;
wire cpu_data_master_granted_cpu_jtag_debug_module;
wire cpu_data_master_qualified_request_cpu_jtag_debug_module;
wire cpu_data_master_read_data_valid_cpu_jtag_debug_module;
wire cpu_data_master_requests_cpu_jtag_debug_module;
wire cpu_data_master_saved_grant_cpu_jtag_debug_module;
wire cpu_instruction_master_arbiterlock;
wire cpu_instruction_master_continuerequest;
wire cpu_instruction_master_granted_cpu_jtag_debug_module;
wire cpu_instruction_master_qualified_request_cpu_jtag_debug_module;
wire cpu_instruction_master_read_data_valid_cpu_jtag_debug_module;
wire cpu_instruction_master_requests_cpu_jtag_debug_module;
wire cpu_instruction_master_saved_grant_cpu_jtag_debug_module;
wire [ 8: 0] cpu_jtag_debug_module_address;
wire cpu_jtag_debug_module_allgrants;
wire cpu_jtag_debug_module_allow_new_arb_cycle;
wire cpu_jtag_debug_module_any_continuerequest;
reg [ 1: 0] cpu_jtag_debug_module_arb_addend;
wire cpu_jtag_debug_module_arb_counter_enable;
reg [ 2: 0] cpu_jtag_debug_module_arb_share_counter;
wire [ 2: 0] cpu_jtag_debug_module_arb_share_counter_next_value;
wire [ 2: 0] cpu_jtag_debug_module_arb_share_set_values;
wire [ 1: 0] cpu_jtag_debug_module_arb_winner;
wire cpu_jtag_debug_module_arbitration_holdoff_internal;
wire cpu_jtag_debug_module_beginbursttransfer_internal;
wire cpu_jtag_debug_module_begins_xfer;
wire cpu_jtag_debug_module_begintransfer;
wire [ 3: 0] cpu_jtag_debug_module_byteenable;
wire cpu_jtag_debug_module_chipselect;
wire [ 3: 0] cpu_jtag_debug_module_chosen_master_double_vector;
wire [ 1: 0] cpu_jtag_debug_module_chosen_master_rot_left;
wire cpu_jtag_debug_module_debugaccess;
wire cpu_jtag_debug_module_end_xfer;
wire cpu_jtag_debug_module_firsttransfer;
wire [ 1: 0] cpu_jtag_debug_module_grant_vector;
wire cpu_jtag_debug_module_in_a_read_cycle;
wire cpu_jtag_debug_module_in_a_write_cycle;
wire [ 1: 0] cpu_jtag_debug_module_master_qreq_vector;
wire [ 31: 0] cpu_jtag_debug_module_readdata_from_sa;
wire cpu_jtag_debug_module_reset;
wire cpu_jtag_debug_module_reset_n;
wire cpu_jtag_debug_module_resetrequest_from_sa;
reg [ 1: 0] cpu_jtag_debug_module_saved_chosen_master_vector;
reg cpu_jtag_debug_module_slavearbiterlockenable;
wire cpu_jtag_debug_module_waits_for_read;
wire cpu_jtag_debug_module_waits_for_write;
wire cpu_jtag_debug_module_write;
wire [ 31: 0] cpu_jtag_debug_module_writedata;
reg d1_cpu_jtag_debug_module_end_xfer;
reg d1_reasons_to_wait;
wire in_a_read_cycle;
wire in_a_write_cycle;
reg last_cycle_cpu_data_master_granted_slave_cpu_jtag_debug_module;
reg last_cycle_cpu_instruction_master_granted_slave_cpu_jtag_debug_module;
wire wait_for_cpu_jtag_debug_module_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else if (1)
d1_reasons_to_wait <= ~cpu_jtag_debug_module_end_xfer;
end
assign cpu_jtag_debug_module_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_cpu_jtag_debug_module | cpu_instruction_master_qualified_request_cpu_jtag_debug_module));
assign cpu_data_master_requests_cpu_jtag_debug_module = ({cpu_data_master_address_to_slave[26 : 11] , 11'b0} == 27'h2220000) & (cpu_data_master_read | cpu_data_master_write);
//assign cpu_jtag_debug_module_readdata_from_sa = cpu_jtag_debug_module_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign cpu_jtag_debug_module_readdata_from_sa = cpu_jtag_debug_module_readdata;
//cpu_jtag_debug_module_arb_share_counter set values, which is an e_mux
assign cpu_jtag_debug_module_arb_share_set_values = 1;
//cpu_jtag_debug_module_arb_share_counter_next_value assignment, which is an e_assign
assign cpu_jtag_debug_module_arb_share_counter_next_value = cpu_jtag_debug_module_firsttransfer ? (cpu_jtag_debug_module_arb_share_set_values - 1) : |cpu_jtag_debug_module_arb_share_counter ? (cpu_jtag_debug_module_arb_share_counter - 1) : 0;
//cpu_jtag_debug_module_allgrants all slave grants, which is an e_mux
assign cpu_jtag_debug_module_allgrants = |cpu_jtag_debug_module_grant_vector |
|cpu_jtag_debug_module_grant_vector |
|cpu_jtag_debug_module_grant_vector |
|cpu_jtag_debug_module_grant_vector;
//cpu_jtag_debug_module_end_xfer assignment, which is an e_assign
assign cpu_jtag_debug_module_end_xfer = ~(cpu_jtag_debug_module_waits_for_read | cpu_jtag_debug_module_waits_for_write);
//cpu_jtag_debug_module_arb_share_counter arbitration counter enable, which is an e_assign
assign cpu_jtag_debug_module_arb_counter_enable = cpu_jtag_debug_module_end_xfer & cpu_jtag_debug_module_allgrants;
//cpu_jtag_debug_module_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_jtag_debug_module_arb_share_counter <= 0;
else if (cpu_jtag_debug_module_arb_counter_enable)
cpu_jtag_debug_module_arb_share_counter <= cpu_jtag_debug_module_arb_share_counter_next_value;
end
//cpu_jtag_debug_module_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_jtag_debug_module_slavearbiterlockenable <= 0;
else if (|cpu_jtag_debug_module_master_qreq_vector & cpu_jtag_debug_module_end_xfer)
cpu_jtag_debug_module_slavearbiterlockenable <= |cpu_jtag_debug_module_arb_share_counter_next_value;
end
//cpu/data_master cpu/jtag_debug_module arbiterlock, which is an e_assign
assign cpu_data_master_arbiterlock = cpu_jtag_debug_module_slavearbiterlockenable & cpu_data_master_continuerequest;
//cpu/instruction_master cpu/jtag_debug_module arbiterlock, which is an e_assign
assign cpu_instruction_master_arbiterlock = cpu_jtag_debug_module_slavearbiterlockenable & cpu_instruction_master_continuerequest;
//cpu/instruction_master granted cpu/jtag_debug_module last time, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
last_cycle_cpu_instruction_master_granted_slave_cpu_jtag_debug_module <= 0;
else if (1)
last_cycle_cpu_instruction_master_granted_slave_cpu_jtag_debug_module <= cpu_instruction_master_saved_grant_cpu_jtag_debug_module ? 1 : (cpu_jtag_debug_module_arbitration_holdoff_internal | ~cpu_instruction_master_requests_cpu_jtag_debug_module) ? 0 : last_cycle_cpu_instruction_master_granted_slave_cpu_jtag_debug_module;
end
//cpu_instruction_master_continuerequest continued request, which is an e_mux
assign cpu_instruction_master_continuerequest = last_cycle_cpu_instruction_master_granted_slave_cpu_jtag_debug_module & cpu_instruction_master_requests_cpu_jtag_debug_module;
//cpu_jtag_debug_module_any_continuerequest at least one master continues requesting, which is an e_mux
assign cpu_jtag_debug_module_any_continuerequest = cpu_instruction_master_continuerequest |
cpu_data_master_continuerequest;
assign cpu_data_master_qualified_request_cpu_jtag_debug_module = cpu_data_master_requests_cpu_jtag_debug_module & ~(cpu_instruction_master_arbiterlock);
//cpu_jtag_debug_module_writedata mux, which is an e_mux
assign cpu_jtag_debug_module_writedata = cpu_data_master_writedata;
//mux cpu_jtag_debug_module_debugaccess, which is an e_mux
assign cpu_jtag_debug_module_debugaccess = cpu_data_master_debugaccess;
assign cpu_instruction_master_requests_cpu_jtag_debug_module = ({cpu_instruction_master_address_to_slave[26 : 11] , 11'b0} == 27'h2220000) & (cpu_instruction_master_read);
//cpu/data_master granted cpu/jtag_debug_module last time, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
last_cycle_cpu_data_master_granted_slave_cpu_jtag_debug_module <= 0;
else if (1)
last_cycle_cpu_data_master_granted_slave_cpu_jtag_debug_module <= cpu_data_master_saved_grant_cpu_jtag_debug_module ? 1 : (cpu_jtag_debug_module_arbitration_holdoff_internal | ~cpu_data_master_requests_cpu_jtag_debug_module) ? 0 : last_cycle_cpu_data_master_granted_slave_cpu_jtag_debug_module;
end
//cpu_data_master_continuerequest continued request, which is an e_mux
assign cpu_data_master_continuerequest = last_cycle_cpu_data_master_granted_slave_cpu_jtag_debug_module & cpu_data_master_requests_cpu_jtag_debug_module;
assign cpu_instruction_master_qualified_request_cpu_jtag_debug_module = cpu_instruction_master_requests_cpu_jtag_debug_module & ~((cpu_instruction_master_read & ((cpu_instruction_master_latency_counter != 0) | (|cpu_instruction_master_read_data_valid_ddr_sdram_s1_shift_register))) | cpu_data_master_arbiterlock);
//local readdatavalid cpu_instruction_master_read_data_valid_cpu_jtag_debug_module, which is an e_mux
assign cpu_instruction_master_read_data_valid_cpu_jtag_debug_module = cpu_instruction_master_granted_cpu_jtag_debug_module & cpu_instruction_master_read & ~cpu_jtag_debug_module_waits_for_read;
//allow new arb cycle for cpu/jtag_debug_module, which is an e_assign
assign cpu_jtag_debug_module_allow_new_arb_cycle = ~cpu_data_master_arbiterlock & ~cpu_instruction_master_arbiterlock;
//cpu/instruction_master assignment into master qualified-requests vector for cpu/jtag_debug_module, which is an e_assign
assign cpu_jtag_debug_module_master_qreq_vector[0] = cpu_instruction_master_qualified_request_cpu_jtag_debug_module;
//cpu/instruction_master grant cpu/jtag_debug_module, which is an e_assign
assign cpu_instruction_master_granted_cpu_jtag_debug_module = cpu_jtag_debug_module_grant_vector[0];
//cpu/instruction_master saved-grant cpu/jtag_debug_module, which is an e_assign
assign cpu_instruction_master_saved_grant_cpu_jtag_debug_module = cpu_jtag_debug_module_arb_winner[0] && cpu_instruction_master_requests_cpu_jtag_debug_module;
//cpu/data_master assignment into master qualified-requests vector for cpu/jtag_debug_module, which is an e_assign
assign cpu_jtag_debug_module_master_qreq_vector[1] = cpu_data_master_qualified_request_cpu_jtag_debug_module;
//cpu/data_master grant cpu/jtag_debug_module, which is an e_assign
assign cpu_data_master_granted_cpu_jtag_debug_module = cpu_jtag_debug_module_grant_vector[1];
//cpu/data_master saved-grant cpu/jtag_debug_module, which is an e_assign
assign cpu_data_master_saved_grant_cpu_jtag_debug_module = cpu_jtag_debug_module_arb_winner[1] && cpu_data_master_requests_cpu_jtag_debug_module;
//cpu/jtag_debug_module chosen-master double-vector, which is an e_assign
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -