//------------------------------------------------------------------------------
// This confidential and proprietary software may be used only as authorized by
// a licensing agreement from Altera Corporation.
//
// (C) COPYRIGHT 2004 ALTERA CORPORATION
// ALL RIGHTS RESERVED
//
// The entire notice above must be reproduced on all authorized copies and any
// such reproduction must be pursuant to a licensing agreement from Altera.
//
// Title        : Example top level testbench for ddr_sdram DDR SDRAM Controller
// Project      : DDR SDRAM Controller
//
// File         : ddr_sdram_debug_design_tb.v
//
// Revision     : V3.2.0
//
// Abstract:
// Automatically generated testbench for the 'Example' top level design to allow
// functional and timing simulation.
//
//------------------------------------------------------------------------------
//
// *************** This is a MegaWizard generated file ****************
//
// If you need to edit this file make sure the edits are not inside any 'MEGAWIZARD'
// text insertion areas.
// (between "<< START MEGAWIZARD INSERT" and "<< END MEGAWIZARD INSERT" comments)
//
// Any edits inside these delimiters will be overwritten by the megawizard if you
// re-run it.
//
// If you really need to make changes inside these delimiters then delete
// both 'START' and 'END' delimiters.  This will stop the megawizard updating this
// section again.
//
//----------------------------------------------------------------------------------
// << START MEGAWIZARD INSERT PARAMETER_LIST
// Parameters:
//
// Device Family                      : Cyclone II
// local Interface Data Width         : 32
// MEM_CHIPSELS                       : 1
// MEM_BANK_BITS                      : 2
// MEM_ROW_BITS                       : 13
// MEM_COL_BITS                       : 9
// LOCAL_DATA_BITS                    : 32
// NUM_CLOCK_PAIRS                    : 1
// RTL_ROUNDTRIP_CLOCKS               : 1.0
// CLOCK_TICK_IN_PS                   : 11764
// REGISTERED_DIMM                    : false
// BOARD_DQS_DELAY                    : 550
// BOARD_CLK_DELAY                    : 550
// TINIT_CLOCKS                       : 17000
// << END MEGAWIZARD INSERT PARAMETER_LIST
//----------------------------------------------------------------------------------
// << MEGAWIZARD PARSE FILE DDR3.2.0


`timescale 1 ps/1 ps



// << START MEGAWIZARD INSERT MODULE
module ddr_sdram_debug_design_tb ();
// << END MEGAWIZARD INSERT MODULE

    // << START MEGAWIZARD INSERT PARAMS
    parameter gMEM_CHIPSELS  = 1;
    parameter gMEM_BANK_BITS  = 2;
    parameter gMEM_ROW_BITS  = 13;
    parameter gMEM_COL_BITS  = 9;
    parameter gLOCAL_DATA_BITS  = 32;
    parameter gNUM_CLOCK_PAIRS  = 1;
    parameter RTL_ROUNDTRIP_CLOCKS  = 1.0;
    parameter CLOCK_TICK_IN_PS  = 11764;
    parameter REGISTERED_DIMM  = 1'b0;
    parameter BOARD_DQS_DELAY  = 550;
    parameter BOARD_CLK_DELAY  = 550;
    parameter BOARD_FEDBACKCLK_DELAY  = 2000;

    parameter TINIT_CLOCKS  = 17000;
    // << END MEGAWIZARD INSERT PARAMS

    // set to zero for Gatelevel
    parameter RTL_DELAYS = 1;
    parameter USE_GENERIC_MEMORY_MODEL  = 1'b0;
    parameter REF_CLOCK_TICK_IN_PS  = 30000;

    // delay the incoming DQ & DQS to mimick the SDRAM round trip delay
    //
    parameter D90_DEG_DELAY = CLOCK_TICK_IN_PS / 4; // RTL only
    parameter GATE_BOARD_DQS_DELAY = BOARD_DQS_DELAY * (RTL_DELAYS ? 0 : 1); // Gate level timing only
    parameter GATE_BOARD_CLK_DELAY = BOARD_CLK_DELAY * (RTL_DELAYS ? 0 : 1); // Gate level timing only
    parameter GATE_BOARD_FEDBACKCLK_DELAY = BOARD_FEDBACKCLK_DELAY * (RTL_DELAYS ? 0 : 1); // Gate level timing only
    wire cmd_bus_watcher_enabled;
    reg clk;
    reg clk_n;
    wire #((CLOCK_TICK_IN_PS / 4) * 3 * 1) clk_shifted;
    reg reset_n;
    wire[gMEM_ROW_BITS - 1:0] a;
    wire[gMEM_BANK_BITS - 1:0] ba;
    wire[gMEM_CHIPSELS - 1:0] cs_n;
    wire[gMEM_CHIPSELS - 1:0] cke;
    wire[gMEM_CHIPSELS - 1:0] odt;       //DDR2 only
    wire ras_n;
    wire cas_n;
    wire we_n;
    wire[gLOCAL_DATA_BITS / 16 - 1:0] dm;
    wire[gLOCAL_DATA_BITS / 16 - 1:0] dqs;
    wire[gLOCAL_DATA_BITS / 2 - 1:0] dq;
    wire[gLOCAL_DATA_BITS - 1:0] datain;
    wire[gLOCAL_DATA_BITS - 1:0] dataout;


    wire stratix_dqs_ref_clk;   // only used on stratix to provide external dll reference clock
    wire #(GATE_BOARD_FEDBACKCLK_DELAY * 1) fedback_clk;           // only used in fedback clock mode
    wire[gNUM_CLOCK_PAIRS - 1:0] clk_to_sdram;
    wire[gNUM_CLOCK_PAIRS - 1:0] clk_to_sdram_n;
    wire #(GATE_BOARD_CLK_DELAY * 1) clk_to_ram;
    wire clk_to_ram_n;
    wire[gMEM_ROW_BITS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) a_delayed;
    wire[gMEM_BANK_BITS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) ba_delayed;
    wire[gMEM_CHIPSELS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) cke_delayed;
    wire[gMEM_CHIPSELS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) odt_delayed;  //DDR2 only
    wire[gMEM_CHIPSELS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) cs_n_delayed;
    wire #(GATE_BOARD_CLK_DELAY * 1 + 1) ras_n_delayed;
    wire #(GATE_BOARD_CLK_DELAY * 1 + 1) cas_n_delayed;
    wire #(GATE_BOARD_CLK_DELAY * 1 + 1) we_n_delayed;
    wire[gLOCAL_DATA_BITS / 16 - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) dm_delayed;

    tri [gLOCAL_DATA_BITS / 2 - 1:0] fpga_dq = 100'bz;
    wire [gLOCAL_DATA_BITS / 2 - 1:0] fpga_dq_int = 100'bz;
    wire [gLOCAL_DATA_BITS / 2 - 1:0] fpga_dq_int0 = 100'bz;
    wire [gLOCAL_DATA_BITS / 2 - 1:0] fpga_dq_int1 = 100'bz;
    wire [gLOCAL_DATA_BITS / 2 - 1:0] fpga_dq_int2 = 100'bz;
    wire [gLOCAL_DATA_BITS / 2 - 1:0] fpga_dq_int3 = 100'bz;
    wire [gLOCAL_DATA_BITS / 2 - 1:0] fpga_dq_int4 = 100'bz;
    wire [gLOCAL_DATA_BITS / 2 - 1:0] fpga_dq_int5 = 100'bz;


    tri [gLOCAL_DATA_BITS / 16 - 1:0] fpga_dqs = 100'bz;
    wire [gLOCAL_DATA_BITS / 16 - 1:0] fpga_dqs_int = 100'bz;
    wire [gLOCAL_DATA_BITS / 16 - 1:0] fpga_dqs_int0 = 100'bz;
    wire [gLOCAL_DATA_BITS / 16 - 1:0] fpga_dqs_int1 = 100'bz;
    wire [gLOCAL_DATA_BITS / 16 - 1:0] fpga_dqs_int2 = 100'bz;
    wire [gLOCAL_DATA_BITS / 16 - 1:0] fpga_dqs_int3 = 100'bz;
    wire [gLOCAL_DATA_BITS / 16 - 1:0] fpga_dqs_int4 = 100'bz;
    wire [gLOCAL_DATA_BITS / 16 - 1:0] fpga_dqs_int5 = 100'bz;

    tri [gLOCAL_DATA_BITS / 2 - 1:0] mem_dq = 100'bz;
    tri [gLOCAL_DATA_BITS / 16 - 1:0] mem_dqs = 100'bz;


    reg dqs_oe = 1'b0;
    reg dqs_active = 1'b0;

    reg dq_oe = 1'b0;
    reg dq_active = 1'b0;

    reg dq_lock;
    reg dqs_lock;
    wire[gLOCAL_DATA_BITS / 2 - 1:0] all_dq_z = 100'bz;
    wire[gLOCAL_DATA_BITS / 16 - 1:0] all_dqs_z = 100'bz;

    wire[gMEM_BANK_BITS - 1:0] zero_one; //"01";
    wire test_complete;
    // counter to count the number of sucessful read and write loops
    integer test_complete_count;
    wire pnf;
    wire[gLOCAL_DATA_BITS / 8 - 1:0] pnf_per_byte;
    wire clk_to_buf;
    wire clk_from_buf;


    assign cmd_bus_watcher_enabled = 1'b0;

   // ddr sdram interface

    // << START MEGAWIZARD INSERT ENTITY
    ddr_sdram_debug_design dut (
    // << END MEGAWIZARD INSERT ENTITY
        .clock_source(clk),
        .clk_to_sdram(clk_to_sdram),
        .clk_to_sdram_n(clk_to_sdram_n),
        .reset_n(reset_n),

        // << START MEGAWIZARD INSERT PORT_MAP



        .ddr_cke(cke),
        .ddr_cs_n(cs_n),
        .ddr_ras_n(ras_n),
        .ddr_cas_n(cas_n),
        .ddr_we_n(we_n),
        .ddr_ba(ba),
        .ddr_a(a),
        .ddr_dq(fpga_dq),
        .ddr_dqs(fpga_dqs),
        .ddr_dm(dm),
        // << END MEGAWIZARD INSERT PORT_MAP


        .test_complete(test_complete),
        .pnf_per_byte(pnf_per_byte),
        .pnf(pnf));


    // << START MEGAWIZARD INSERT MEMORY_ARRAY
    // Instantiate an array of 8-bit DDR memories to match the datawidth & chipselect requirements
    // This will need updating to match the memory models you are using.


    generic_ddr_sdram_rtl memory_0_0 (
        .Dq    (mem_dq[8* (0+1) - 1 : 8 * 0]),
        .Dqs   (mem_dqs[0]),
//        .Addr  (a_delayed[13-1: 0]),
        .Addr  (a_delayed[11: 0]),
        .Ba    (ba_delayed),
        .Clk   (clk_to_ram),
        .Clk_n (clk_to_ram_n),
        .Cke   (cke_delayed[0]),
        .Cs_n  (cs_n_delayed[0]),
        .Ras_n (ras_n_delayed),
        .Cas_n (cas_n_delayed),
        .We_n  (we_n_delayed),
        .Dm    (dm_delayed[0])
    );


    generic_ddr_sdram_rtl memory_0_1 (
        .Dq    (mem_dq[8* (1+1) - 1 : 8 * 1]),
        .Dqs   (mem_dqs[1]),
//        .Addr  (a_delayed[13-1: 0]),
        .Addr  (a_delayed[11: 0]),
        .Ba    (ba_delayed),
        .Clk   (clk_to_ram),
        .Clk_n (clk_to_ram_n),
        .Cke   (cke_delayed[0]),
        .Cs_n  (cs_n_delayed[0]),
        .Ras_n (ras_n_delayed),
        .Cas_n (cas_n_delayed),
        .We_n  (we_n_delayed),
        .Dm    (dm_delayed[1])
    );

    // << END MEGAWIZARD INSERT MEMORY_ARRAY


    always
    begin
        clk <= 1'b0 ;
        clk_n <= 1'b1 ;
        while (1'b1)
        begin
            #((CLOCK_TICK_IN_PS / 2) * 1);
            clk <= ~clk ;
            clk_n <= ~clk_n ;
        end
    end

    assign clk_shifted = clk_to_sdram[0] ;
    assign clk_to_ram = clk_to_sdram[0] ;
    assign clk_to_ram_n = ~clk_to_ram ; // mem model ignores clk_n ?

    // << START MEGAWIZARD INSERT FEDBACK_CLOCK_DELAY

    // << END MEGAWIZARD INSERT FEDBACK_CLOCK_DELAY


    initial
    begin
        reset_n <= 1'b0 ;
        @(clk_to_sdram[0]);
        @(clk_to_sdram[0]);
        @(clk_to_sdram[0]);
        @(clk_to_sdram[0]);
        @(clk_to_sdram[0]);
        reset_n <= 1'b1 ;
    end

    // control and data lines = 3 inches
    assign a_delayed = a ;
    assign ba_delayed = ba ;
    assign cke_delayed = cke ;
    assign odt_delayed = odt ;
    assign cs_n_delayed = cs_n ;