-- Generated by DDR SDRAM Controller 3.2.0 [Altera, IP Toolbench v1.2.9 build43]
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
-- Copyright (C) 1991-2005 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.

FUNCTION ddr_sdram
(
	clk,
	write_clk,
	reset_n,
	local_read_req,
	local_write_req,
	local_addr[22..0],
	local_wdata[31..0],
	local_be[3..0]
)
RETURNS (
	local_ready,
	local_rdata[31..0],
	local_rdata_valid,
	clk_to_sdram,
	clk_to_sdram_n,
	ddr_cs_n,
	ddr_cke,
	ddr_a[12..0],
	ddr_ba[1..0],
	ddr_ras_n,
	ddr_cas_n,
	ddr_we_n,
	ddr_dm[1..0],
	ddr_dq[15..0],
	ddr_dqs[1..0]
);