# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic       
# functions, and any output files any of the foregoing           
# (including device programming or simulation files), and any    
# associated documentation or information are expressly subject  
# to the terms and conditions of the Altera Program License      
# Subscription Agreement, Altera MegaCore Function License       
# Agreement, or other applicable license agreement, including,   
# without limitation, that your use is for the sole purpose of   
# programming logic devices manufactured by Altera and sold by   
# Altera or its authorized distributors.  Please refer to the    
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		standard_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 5.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:13:22  FEBRUARY 11, 2005"
set_global_assignment -name LAST_QUARTUS_VERSION 5.0
set_global_assignment -name BDF_FILE ../standard.bdf
set_global_assignment -name POST_FLOW_SCRIPT_FILE "quartus_sh:auto_verify_ddr_timing.tcl"
set_global_assignment -name VHDL_FILE "C:/megacore/ddr_ddr2_sdram-v3.2.0/lib/auk_ddr_tb_functions.vhd"
set_global_assignment -name VHDL_FILE "C:/megacore/ddr_ddr2_sdram-v3.2.0/lib/auk_ddr_functions.vhd"
set_global_assignment -name VHDL_FILE "C:/megacore/ddr_ddr2_sdram-v3.2.0/lib/auk_ddr_input_buf.vhd"
set_global_assignment -name VHDL_FILE "C:/megacore/ddr_ddr2_sdram-v3.2.0/lib/auk_ddr_timers.vhd"
set_global_assignment -name VHDL_FILE "C:/megacore/ddr_ddr2_sdram-v3.2.0/lib/auk_ddr_avalon_if.vhd"
set_global_assignment -name VHDL_FILE "C:/megacore/ddr_ddr2_sdram-v3.2.0/lib/auk_ddr_bank_details.vhd"
set_global_assignment -name VHDL_FILE "C:/megacore/ddr_ddr2_sdram-v3.2.0/lib/auk_ddr_controller.vhd"
set_global_assignment -name VHDL_FILE "C:/megacore/ddr_ddr2_sdram-v3.2.0/lib/auk_ddr_init.vhd"
set_global_assignment -name VHDL_FILE "C:/altera/MegaCore/ddr_ddr2_sdram-v3.2.0/lib/auk_ddr_tb_functions.vhd"
set_global_assignment -name VHDL_FILE "C:/altera/MegaCore/ddr_ddr2_sdram-v3.2.0/lib/auk_ddr_functions.vhd"
set_global_assignment -name VHDL_FILE "C:/altera/MegaCore/ddr_ddr2_sdram-v3.2.0/lib/auk_ddr_input_buf.vhd"
set_global_assignment -name VHDL_FILE "C:/altera/MegaCore/ddr_ddr2_sdram-v3.2.0/lib/auk_ddr_timers.vhd"
set_global_assignment -name VHDL_FILE "C:/altera/MegaCore/ddr_ddr2_sdram-v3.2.0/lib/auk_ddr_avalon_if.vhd"
set_global_assignment -name VHDL_FILE "C:/altera/MegaCore/ddr_ddr2_sdram-v3.2.0/lib/auk_ddr_bank_details.vhd"
set_global_assignment -name VHDL_FILE "C:/altera/MegaCore/ddr_ddr2_sdram-v3.2.0/lib/auk_ddr_controller.vhd"
set_global_assignment -name VHDL_FILE "C:/altera/MegaCore/ddr_ddr2_sdram-v3.2.0/lib/auk_ddr_init.vhd"

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_AD10 -to out_port_from_the_seven_seg_pio[0]
set_location_assignment PIN_AF10 -to out_port_from_the_seven_seg_pio[1]
set_location_assignment PIN_AE10 -to out_port_from_the_seven_seg_pio[2]
set_location_assignment PIN_AE11 -to out_port_from_the_seven_seg_pio[3]
set_location_assignment PIN_AD11 -to out_port_from_the_seven_seg_pio[4]
set_location_assignment PIN_V13 -to out_port_from_the_seven_seg_pio[5]
set_location_assignment PIN_V14 -to out_port_from_the_seven_seg_pio[6]
set_location_assignment PIN_AC11 -to out_port_from_the_seven_seg_pio[7]
set_location_assignment PIN_V11 -to out_port_from_the_seven_seg_pio[8]
set_location_assignment PIN_Y12 -to out_port_from_the_seven_seg_pio[9]
set_location_assignment PIN_AA12 -to out_port_from_the_seven_seg_pio[10]
set_location_assignment PIN_AE12 -to out_port_from_the_seven_seg_pio[11]
set_location_assignment PIN_AD12 -to out_port_from_the_seven_seg_pio[12]
set_location_assignment PIN_AF13 -to out_port_from_the_seven_seg_pio[13]
set_location_assignment PIN_AE13 -to out_port_from_the_seven_seg_pio[14]
set_location_assignment PIN_U12 -to out_port_from_the_seven_seg_pio[15]
set_location_assignment PIN_C25 -to byteenablen_to_the_lan91c111[0]
set_location_assignment PIN_C24 -to byteenablen_to_the_lan91c111[1]
set_location_assignment PIN_D26 -to byteenablen_to_the_lan91c111[2]
set_location_assignment PIN_D25 -to byteenablen_to_the_lan91c111[3]
set_location_assignment PIN_E20 -to ior_n_to_the_lan91c111
set_location_assignment PIN_D16 -to iow_n_to_the_lan91c111
set_location_assignment PIN_AA15 -to irq_from_the_lan91c111
set_location_assignment PIN_E18 -to enet_ads_n
set_location_assignment PIN_E26 -to enet_aen
set_location_assignment PIN_D18 -to ardy_from_the_lan91c111
set_location_assignment PIN_F9 -to ext_flash_enet_bus_address[0]
set_location_assignment PIN_H8 -to ext_flash_enet_bus_address[1]
set_location_assignment PIN_D11 -to ext_flash_enet_bus_address[2]
set_location_assignment PIN_E8 -to ext_flash_enet_bus_address[3]
set_location_assignment PIN_B14 -to ext_flash_enet_bus_address[4]
set_location_assignment PIN_A14 -to ext_flash_enet_bus_address[5]
set_location_assignment PIN_F14 -to ext_flash_enet_bus_address[6]
set_location_assignment PIN_G14 -to ext_flash_enet_bus_address[7]
set_location_assignment PIN_F13 -to ext_flash_enet_bus_address[8]
set_location_assignment PIN_G13 -to ext_flash_enet_bus_address[9]
set_location_assignment PIN_C15 -to ext_flash_enet_bus_address[10]
set_location_assignment PIN_B15 -to ext_flash_enet_bus_address[11]
set_location_assignment PIN_B16 -to ext_flash_enet_bus_address[12]
set_location_assignment PIN_C16 -to ext_flash_enet_bus_address[13]
set_location_assignment PIN_D15 -to ext_flash_enet_bus_address[14]
set_location_assignment PIN_E15 -to ext_flash_enet_bus_address[15]
set_location_assignment PIN_H15 -to ext_flash_enet_bus_address[16]
set_location_assignment PIN_H16 -to ext_flash_enet_bus_address[17]
set_location_assignment PIN_A17 -to ext_flash_enet_bus_address[18]
set_location_assignment PIN_B17 -to ext_flash_enet_bus_address[19]
set_location_assignment PIN_G15 -to ext_flash_enet_bus_address[20]
set_location_assignment PIN_F15 -to ext_flash_enet_bus_address[21]
set_location_assignment PIN_F16 -to ext_flash_enet_bus_address[22]
set_location_assignment PIN_G16 -to ext_flash_enet_bus_address[23]
set_location_assignment PIN_D8 -to ext_flash_enet_bus_data[0]
set_location_assignment PIN_C8 -to ext_flash_enet_bus_data[1]
set_location_assignment PIN_F10 -to ext_flash_enet_bus_data[2]
set_location_assignment PIN_G10 -to ext_flash_enet_bus_data[3]
set_location_assignment PIN_D9 -to ext_flash_enet_bus_data[4]
set_location_assignment PIN_C9 -to ext_flash_enet_bus_data[5]
set_location_assignment PIN_B8 -to ext_flash_enet_bus_data[6]
set_location_assignment PIN_A8 -to ext_flash_enet_bus_data[7]
set_location_assignment PIN_H11 -to ext_flash_enet_bus_data[8]
set_location_assignment PIN_H12 -to ext_flash_enet_bus_data[9]
set_location_assignment PIN_F11 -to ext_flash_enet_bus_data[10]
set_location_assignment PIN_E10 -to ext_flash_enet_bus_data[11]
set_location_assignment PIN_B9 -to ext_flash_enet_bus_data[12]
set_location_assignment PIN_A9 -to ext_flash_enet_bus_data[13]
set_location_assignment PIN_C10 -to ext_flash_enet_bus_data[14]
set_location_assignment PIN_D10 -to ext_flash_enet_bus_data[15]