mem_type=ddr_sdram
tcl_pin_file=c:/altera/MegaCore/ddr_ddr2_sdram-v3.2.0/lib/ip_toolbench/../../constraints/sopc_cycloneii_nios_pins.tcl
megawizard_version=3.2.0
memory_device=Nios_Development_Board,_Cyclone_II_(EP2C35)
override_resync_phase= 180
override_capture_phase= -1
override_postamble_phase= 90
manual_hierarchy_control=false
parse_example_design=false
pf_pin_load_on_dq=4
pf_pin_load_on_cmd=2
pf_pin_load_on_clk=2
clockfeedback_in_pin_name=fedback_clock_in
fedback_clock_mode=false
tpd_clockfeedback_trace_nom=2000
family=cycloneii
local_data_bits=32
mem_dq_per_dqs=8
mem_chip_bits=0
enable_capture_clk=false
enable_resynch_clk=true
chosen_resynch_clk=clk
chosen_resynch_edge=falling
chosen_resynch_cycle=1
inter_resynch=false
chosen_capture_clk=write_clk
chosen_capture_edge=rising
chosen_postamble_clk=write_clk
chosen_postamble_edge=falling
chosen_postamble_cycle=1
inter_postamble=false
pipeline_readdata=true
postamble_regs=1
stratix_undelayeddqsout_insert_buffers=0
clock_period_in_ps=11764
dqs_phase=
local_avalon_if=true
mem_chipsels=1
mem_bank_bits=2
mem_row_bits=13
mem_col_bits=9
local_burst_len=1
local_burst_len_bits=1
user_refresh=false
num_output_clocks=1
toplevel_name=ddr_sdram_debug_design
wrapper_name=ddr_sdram
ddr_pin_prefix=ddr_
//From old ddr_settings file
current_script_working_dir=c:/altera/MegaCore/ddr_ddr2_sdram-v3.2.0/system_timing
current_quartus_project_dir=C:/designs/cf_tests/to_nios_forum/std_cf_2c35
enable_postamble=true
quartus_project_name=standard
quartus_version=5.0
device=EP2C35
speed_grade=C6
clock_freq_in_mhz=85.0
cas_latency=2.5
ddr_mode=normal
use_dedicated_pll_output_as_clock=0
dll_ref_clock__switched_off_during_reads=true
tPD_clock_trace_NOM=550
tPD_dqs_trace_total_NOM=550
pcb_delay_var_percent=5
board_tSKEW_data_group=50
tPD_fedback_clock_NOM=2000
memory_tDQSQ=450
memory_tQHS=550
memory_tDQSCK=600
memory_tAC=700
memory_fmax_at_cl5=0.0
memory_fmax_at_cl4=0.0
memory_fmax_at_cl3=166.6667
memory_fmax_at_cl25=166.6667
memory_fmax_at_cl2=133.3333
memory_tCK_MAX=13000
memory_tDS=450
memory_tDH=450
memory_percent_tDQSS=25
override_resynch_was_used=false
override_capture_was_used=false
override_postamble_was_used=false
dqs_delay_cyclone=47
project_path=C:/designs/cf_tests/to_nios_forum/std_cf_2c35
wrapper_path=C:/designs/cf_tests/to_nios_forum/std_cf_2c35
mw_path=c:/altera/MegaCore/ddr_ddr2_sdram-v3.2.0/system_timing
//From user_assignments.txt
memory_type=ddr_sdram
memory_width=16
package=F672
instance_name_1=ddr_sdram
v=0
byte_groups = 1L 3L
buffer_DLL_delay_output=false
use_dqs_for_read=true
language=verilog
tinit_clocks=17000
rtl_roundtrip_clocks=1.0
variation_path=Automatically extracted by Quartus synthesis|
clock_pos_pin_name=clk_to_sdram[0]
clock_neg_pin_name=clk_to_sdram_n[0]
stratixii_dqs_phase=9999
stratixii_dll_delay_buffer_mode=undefined
stratixii_dqs_out_mode=undefined
stratixii_dll_delay_chain_length=99
reg_dimm=false
migratable_bytegroups=true
chosen_resynch_cycle=1
chosen_postamble_phase=90
dqs_cram_cyclone=47
chosen_resynch_phase=180
family_is_stratix=false
chosen_postamble_cycle=1
family_is_stratix2=false
family_is_cyclone2=true
best_dqs_shift_setting=47