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// synthesis translate_off
`timescale 1ps / 1ps
// synthesis translate_on
//------------------------------------------------------------------------------
//This confidential and proprietary software may be used only as authorized by
//a licensing agreement from Altera Corporation.
//(C) COPYRIGHT 2004 ALTERA CORPORATION
//ALL RIGHTS RESERVED
//The entire notice above must be reproduced on all authorized copies and any
//such reproduction must be pursuant to a licensing agreement from Altera.
//Title        : Datapath for the Altera DDR SDRAM Controller
//Project      : DDR SDRAM Controller
//File         : ddr_sdram_ddr_dqs_group.v
//Revision     : V3.2.0
//Abstract:
//This file contains the datapath for the DDR SDRAM Controller.
//------------------------------------------------------------------------------
//Parameters:
//Device Family                      : Cyclone II
//DQ_PER_DQS                         : 8
//NON-DQS MODE                       : false
//use Resynch clock                  : true
//Resynch clock edge                 : falling
//Postamble Clock Edge               : falling
//Postamble Clock Cycle              : 1
//Intermediate Resynch               : false
//Intermediate Postamble             : false
//Pipeline read Data                 : true
//Enable Postamble Logic             : true
//Postamble Regs Per DQS             : 1
//Stratix Insert DQS delay buffers   : 0
//------------------------------------------------------------------------------
module ddr_sdram_auk_ddr_dqs_group (
                                     // inputs:
                                      capture_clk,
                                      clk,
                                      control_be,
                                      control_doing_rd,
                                      control_doing_wr,
                                      control_dqs_burst,
                                      control_wdata,
                                      control_wdata_valid,
                                      postamble_clk,
                                      reset_n,
                                      resynch_clk,
                                      write_clk,

                                     // outputs:
                                      control_rdata,
                                      ddr_dm,
                                      ddr_dq,
                                      ddr_dqs
                                   );

  parameter gINTER_RESYNCH = "false";
  parameter gPIPELINE_READDATA = "true";
  parameter gPOSTAMBLE_REGS = 1;
  parameter gMEM_DQ_PER_DQS = 8;
  parameter gINTER_POSTAMBLE = "false";
  parameter gPOSTAMBLE_CYCLE = 1;


  output  [ 15: 0] control_rdata;
  output           ddr_dm;
  inout   [  7: 0] ddr_dq;
  inout            ddr_dqs;
  input            capture_clk;
  input            clk;
  input   [  1: 0] control_be;
  input            control_doing_rd;
  input            control_doing_wr;
  input            control_dqs_burst;
  input   [ 15: 0] control_wdata;
  input            control_wdata_valid;
  input            postamble_clk;
  input            reset_n;
  input            resynch_clk;
  input            write_clk;

  wire             ZERO;
  wire    [  7: 0] ZEROS;
  wire    [  1: 0] be;
  wire    [ 15: 0] control_rdata;
  wire             ddr_dm;
  wire    [  7: 0] ddr_dq;
  wire             ddr_dqs;
  wire    [  3: 0] delayed_dqs;
  reg     [  1: 0] dm_out;
  wire             doing_rd;
  reg              doing_rd_delayed;
  reg     [  2: 0] doing_rd_pipe;
  wire             doing_wr;
  reg              doing_wr_r;
  wire             dq_capture_clk;
  wire    [  7: 0] dq_captured_falling;
  wire    [  7: 0] dq_captured_rising;
  reg     [  0: 0] dq_enable;
  reg     [  0: 0] dq_enable_reset;
  reg              dq_oe;
  wire             dqs_burst;
  reg              dqs_burst_r;
  wire    [  0: 0] dqs_clk;
  wire             dqs_oe;
  reg     [  0: 0] dqs_oe_r;
  wire             dqs_postamble_clk;
  wire    [ 15: 0] inter_rdata;
  wire    [  0: 0] not_dqs_clk;
  reg     [ 15: 0] rdata;
  wire             reset;
  reg     [ 15: 0] resynched_data;
  wire             tmp_dmout0;
  wire             tmp_dmout1;
  wire    [ 15: 0] wdata;
  reg     [ 15: 0] wdata_r;
  wire             wdata_valid;
  wire    [  0: 0] wire_dqs_clkctrl_outclk;
  //


  assign ZERO = 1'b0;
  assign ZEROS = 0;
  assign reset = ~reset_n;
  assign not_dqs_clk = ~dqs_clk;
  // rename user i/f signals, outputs
  assign control_rdata = rdata;

  // rename user i/f signals, inputs
  assign wdata = control_wdata;

  assign wdata_valid = control_wdata_valid;
  assign doing_wr = control_doing_wr;
  assign doing_rd = control_doing_rd;
  assign be = control_be;
  assign dqs_burst = control_dqs_burst;
  //-----------------------------------------------------------------------------
  //DQS pin and its logic
  //Generate the output enable for DQS from the signal that indicates we're
  //doing a write. The DQS burst signal is generated by the controller to keep
  //the DQS toggling for the required burst length.
  //-----------------------------------------------------------------------------

  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
        begin
          dqs_oe_r <= 1'b0;
          doing_wr_r <= 1'b0;
          dqs_burst_r <= 1'b0;
        end
      else 
        begin
          dqs_oe_r <= dqs_oe;
          doing_wr_r <= doing_wr;
          dqs_burst_r <= dqs_burst;
        end
    end


  assign dqs_oe = doing_wr | dqs_burst;
  //

  altddio_bidir dqs_io
    (
      .aclr (reset),
      .aset (),
      .combout (dqs_clk),
      .datain_h (dqs_oe_r),
      .datain_l (ZEROS[0]),
      .dataout_h (),
      .dataout_l (),
      .inclock (1'b1),
      .inclocken (1'b1),
      .oe (dqs_oe),
      .outclock (clk),
      .outclocken (1'b1),
      .padio (ddr_dqs)
    );

  defparam dqs_io.extend_oe_disable = "ON",
           dqs_io.implement_input_in_lcell = "UNUSED",
           dqs_io.intended_device_family = "Cyclone II",
           dqs_io.invert_output = "OFF",
           dqs_io.lpm_hint = "UNUSED",
           dqs_io.lpm_type = "altddio_bidir",
           dqs_io.oe_reg = "REGISTERED",
           dqs_io.power_up_high = "OFF",
           dqs_io.width = 1;

  cycloneii_clk_delay_ctrl dqs_delay_ctrl
    (
      .clk (dqs_clk),
      .clkout (delayed_dqs[0])
    );

  defparam dqs_delay_ctrl.delay_chain = "47",
           dqs_delay_ctrl.delay_chain_mode = "static",
           dqs_delay_ctrl.lpm_type = "cycloneii_clk_delay_ctrl";

  assign delayed_dqs[3 : 1] = {1'b0,1'b0,1'b0};
  cycloneii_clkctrl dqs_clkctrl
    (
      .clkselect (2'b00),
      .ena (dq_enable),
      .inclk (delayed_dqs),
      .outclk (wire_dqs_clkctrl_outclk)
    );

  defparam dqs_clkctrl.ena_register_mode = "none",
           dqs_clkctrl.lpm_type = "cycloneii_clkctrl";

  //-----------------------------------------------------------------------------
  //DM pins and their logic
  //Although these don't get tristated like DQ, they do share the same IO timing.
  //-----------------------------------------------------------------------------
  assign tmp_dmout0 = dm_out[0];
  assign tmp_dmout1 = dm_out[1];
  altddio_out dm_pin
    (
      .aclr (reset),
      .aset (),
      .datain_h (tmp_dmout0),
      .datain_l (tmp_dmout1),
      .dataout (ddr_dm),
      .oe (1'b1),
      .outclock (write_clk),
      .outclocken (1'b1)
    );

  defparam dm_pin.extend_oe_disable = "UNUSED",
           dm_pin.intended_device_family = "Cyclone II",
           dm_pin.invert_output = "OFF",
           dm_pin.lpm_hint = "UNUSED",
           dm_pin.lpm_type = "altddio_out",
           dm_pin.oe_reg = "UNUSED",
           dm_pin.power_up_high = "OFF",
           dm_pin.width = 1;

  //-----------------------------------------------------------------------------
  //Data mask registers
  //These are the last registers before the registers in the altddio_out. They
  //are clocked off the system clock but feed registers which are clocked off the
  //write clock, so their output is the beginning of 3/4 cycle path.
  //-----------------------------------------------------------------------------
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          dm_out <= {2{1'b1}};
      else if (doing_wr)
          // don't latch in data unless it's valid
          dm_out <= ~be;

      else 
        dm_out <= {2{1'b1}};
    end


  //-----------------------------------------------------------------------------
  //Logic to disable the capture registers (particularly during DQS postamble)
  //The output of the dq_enable_reset register holds the dq_enable register in
  //reset (which *enables* the dq capture registers). The controller releases
  //the dq_enable register so that it is clocked by the last falling edge of the
  //read dqs signal. This disables the dq capture registers during and after the
  //dqs postamble so that the output of the dq capture registers can be safely
  //resynchronised.
  //Postamble Clock Cycle  : 1
  //Postamble Clock Edge   : falling
  //Postamble Regs Per DQS : 1
  //-----------------------------------------------------------------------------

  //Critical registers clocked on the falling edge of the DQS to
  //disable the DQ capture registers during the DQS postamble
  always @(posedge dqs_postamble_clk or posedge dq_enable_reset)
    begin
      if (dq_enable_reset == 1)
          dq_enable <= 1'b1;
      else 
        dq_enable <= 1'b0;
    end


  //Use a falling edge for postamble
  //The registers which generate the reset signal to the above registers
  //Can be clocked off the resynch or system clock
  always @(negedge postamble_clk or negedge reset_n)
    begin
      if (reset_n == 0)
          dq_enable_reset <= 1'b0;
      else 
        dq_enable_reset <= doing_rd_delayed;
    end


  //pipeline the doing_rd signal to enable and disable the DQ capture regs at the right time
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)