{
            width = "1";
            direction = "output";
            Is_Enabled = "0";
         }
         PORT jtag_debug_offchip_trace_clk
         {
            width = "1";
            direction = "output";
            Is_Enabled = "0";
         }
         PORT jtag_debug_offchip_trace_data
         {
            width = "18";
            direction = "output";
            Is_Enabled = "0";
         }
         PORT clkx2
         {
            width = "1";
            direction = "input";
            Is_Enabled = "0";
         }
      }
      SIMULATION 
      {
         DISPLAY 
         {
            SIGNAL aaa
            {
               format = "Logic";
               name = "i_readdata";
               radix = "hexadecimal";
            }
            SIGNAL aab
            {
               format = "Logic";
               name = "i_readdatavalid";
               radix = "hexadecimal";
            }
            SIGNAL aac
            {
               format = "Logic";
               name = "i_waitrequest";
               radix = "hexadecimal";
            }
            SIGNAL aad
            {
               format = "Logic";
               name = "i_address";
               radix = "hexadecimal";
            }
            SIGNAL aae
            {
               format = "Logic";
               name = "i_read";
               radix = "hexadecimal";
            }
            SIGNAL aaf
            {
               format = "Logic";
               name = "clk";
               radix = "hexadecimal";
            }
            SIGNAL aag
            {
               format = "Logic";
               name = "reset_n";
               radix = "hexadecimal";
            }
            SIGNAL aah
            {
               format = "Logic";
               name = "d_readdata";
               radix = "hexadecimal";
            }
            SIGNAL aai
            {
               format = "Logic";
               name = "d_waitrequest";
               radix = "hexadecimal";
            }
            SIGNAL aaj
            {
               format = "Logic";
               name = "d_irq";
               radix = "hexadecimal";
            }
            SIGNAL aak
            {
               format = "Logic";
               name = "d_address";
               radix = "hexadecimal";
            }
            SIGNAL aal
            {
               format = "Logic";
               name = "d_byteenable";
               radix = "hexadecimal";
            }
            SIGNAL aam
            {
               format = "Logic";
               name = "d_read";
               radix = "hexadecimal";
            }
            SIGNAL aan
            {
               format = "Logic";
               name = "d_write";
               radix = "hexadecimal";
            }
            SIGNAL aao
            {
               format = "Logic";
               name = "d_writedata";
               radix = "hexadecimal";
            }
            SIGNAL aap
            {
               format = "Divider";
               name = "base pipeline";
               radix = "";
            }
            SIGNAL aaq
            {
               format = "Logic";
               name = "clk";
               radix = "hexadecimal";
            }
            SIGNAL aar
            {
               format = "Logic";
               name = "reset_n";
               radix = "hexadecimal";
            }
            SIGNAL aas
            {
               format = "Logic";
               name = "M_stall";
               radix = "hexadecimal";
            }
            SIGNAL aat
            {
               format = "Logic";
               name = "F_pcb_nxt";
               radix = "hexadecimal";
            }
            SIGNAL aau
            {
               format = "Logic";
               name = "F_pcb";
               radix = "hexadecimal";
            }
            SIGNAL aav
            {
               format = "Logic";
               name = "D_pcb";
               radix = "hexadecimal";
            }
            SIGNAL aaw
            {
               format = "Logic";
               name = "E_pcb";
               radix = "hexadecimal";
            }
            SIGNAL aax
            {
               format = "Logic";
               name = "M_pcb";
               radix = "hexadecimal";
            }
            SIGNAL aay
            {
               format = "Logic";
               name = "W_pcb";
               radix = "hexadecimal";
            }
            SIGNAL aaz
            {
               format = "Logic";
               name = "F_vinst";
               radix = "ascii";
            }
            SIGNAL aba
            {
               format = "Logic";
               name = "D_vinst";
               radix = "ascii";
            }
            SIGNAL abb
            {
               format = "Logic";
               name = "E_vinst";
               radix = "ascii";
            }
            SIGNAL abc
            {
               format = "Logic";
               name = "M_vinst";
               radix = "ascii";
            }
            SIGNAL abd
            {
               format = "Logic";
               name = "W_vinst";
               radix = "ascii";
            }
            SIGNAL abe
            {
               format = "Logic";
               name = "F_inst_ram_hit";
               radix = "hexadecimal";
            }
            SIGNAL abf
            {
               format = "Logic";
               name = "F_issue";
               radix = "hexadecimal";
            }
            SIGNAL abg
            {
               format = "Logic";
               name = "F_kill";
               radix = "hexadecimal";
            }
            SIGNAL abh
            {
               format = "Logic";
               name = "D_kill";
               radix = "hexadecimal";
            }
            SIGNAL abi
            {
               format = "Logic";
               name = "D_refetch";
               radix = "hexadecimal";
            }
            SIGNAL abj
            {
               format = "Logic";
               name = "D_issue";
               radix = "hexadecimal";
            }
            SIGNAL abk
            {
               format = "Logic";
               name = "D_valid";
               radix = "hexadecimal";
            }
            SIGNAL abl
            {
               format = "Logic";
               name = "E_valid";
               radix = "hexadecimal";
            }
            SIGNAL abm
            {
               format = "Logic";
               name = "M_valid";
               radix = "hexadecimal";
            }
            SIGNAL abn
            {
               format = "Logic";
               name = "W_valid";
               radix = "hexadecimal";
            }
            SIGNAL abo
            {
               format = "Logic";
               name = "W_wr_dst_reg";
               radix = "hexadecimal";
            }
            SIGNAL abp
            {
               format = "Logic";
               name = "W_dst_regnum";
               radix = "hexadecimal";
            }
            SIGNAL abq
            {
               format = "Logic";
               name = "W_wr_data";
               radix = "hexadecimal";
            }
            SIGNAL abr
            {
               format = "Logic";
               name = "F_en";
               radix = "hexadecimal";
            }
            SIGNAL abs
            {
               format = "Logic";
               name = "D_en";
               radix = "hexadecimal";
            }
            SIGNAL abt
            {
               format = "Logic";
               name = "E_en";
               radix = "hexadecimal";
            }
            SIGNAL abu
            {
               format = "Logic";
               name = "M_en";
               radix = "hexadecimal";
            }
            SIGNAL abv
            {
               format = "Logic";
               name = "F_iw";
               radix = "hexadecimal";
            }
            SIGNAL abw
            {
               format = "Logic";
               name = "D_iw";
               radix = "hexadecimal";
            }
            SIGNAL abx
            {
               format = "Logic";
               name = "E_iw";
               radix = "hexadecimal";
            }
            SIGNAL aby
            {
               format = "Logic";
               name = "E_valid_prior_to_hbreak";
               radix = "hexadecimal";
            }
            SIGNAL abz
            {
               format = "Logic";
               name = "M_pipe_flush_nxt";
               radix = "hexadecimal";
            }
            SIGNAL aca
            {
               format = "Logic";
               name = "M_pipe_flush_baddr_nxt";
               radix = "hexadecimal";
            }
            SIGNAL acb
            {
               format = "Logic";
               name = "M_status_reg_pie";
               radix = "hexadecimal";
            }
            SIGNAL acc
            {
               format = "Logic";
               name = "M_ienable_reg";
               radix = "hexadecimal";
            }
            SIGNAL acd
            {
               format = "Logic";
               name = "intr_req";
               radix = "hexadecimal";
            }
         }
      }
   }
   MODULE ext_ssram_bus
   {
      class = "altera_avalon_tri_state_bridge";
      class_version = "2.0";
      SLAVE avalon_slave
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Bridges_To = "tristate_master";
            Base_Address = "N/A";
            Has_IRQ = "0";
            IRQ = "N/A";
            Register_Outgoing_Signals = "1";
            Register_Incoming_Signals = "1";
            MASTERED_BY cpu/instruction_master
            {
               priority = "8";
            }
            MASTERED_BY cpu/data_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "NC";
            }
         }
      }
      MASTER tristate_master
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon_tristate";
            Bridges_To = "avalon_slave";
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "1";
         Is_Enabled = "1";
         Is_Bridge = "1";
         Clock_Source = "clk_85";
         View 
         {
            MESSAGES 
            {
            }
            Is_Collapsed = "1";
         }
         Top_Level_Ports_Are_Enumerated = "1";
      }
   }
   MODULE ext_ssram
   {
      class = "altera_avalon_cy7c1380_ssram";
      class_version = "1.0";