?? std_2c35.ptf
字號:
iss_model_name = "altera_memory";
HDL_INFO
{
}
WIZARD_SCRIPT_ARGUMENTS
{
sram_memory_size = "2048";
sram_memory_units = "1024";
ssram_data_width = "32";
MAKE
{
TARGET delete_placeholder_warning
{
ext_ssram
{
Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
Is_Phony = "1";
Target_File = "do_delete_placeholder_warning";
}
}
TARGET sim
{
ext_ssram
{
Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";
Command3 = "touch $(SIMDIR)/dummy_file";
Dependency = "$(ELF)";
Target_File = "$(SIMDIR)/dummy_file";
}
}
}
ssram_read_latency = "2";
simulation_model_num_lanes = "4";
}
SLAVE s1
{
PORT_WIRING
{
PORT address
{
direction = "input";
is_shared = "0";
type = "address";
width = "19";
lsb = "2";
BOARD_COMPONENT altera_nios_dev_board_cyclone_2c35
{
component_pin = "U74.37,U74.36,U74.35,U74.34,U74.33,U74.32,U74.42,U74.43,U74.44,U74.45,U74.46,U74.47,U74.48,U74.49,U74.50,U74.81,U74.82,U74.99,U74.100";
pin_assignment = "G5,G6,C2,C3,B2,B3,L9,F7,L10,J5,L4,C6,A4,B4,A5,B5,B6,A6,C4";
}
}
PORT adsc_n
{
direction = "input";
is_shared = "0";
type = "begintransfer_n";
width = "1";
BOARD_COMPONENT altera_nios_dev_board_cyclone_2c35
{
component_pin = "U74.85";
pin_assignment = "G9";
}
}
PORT bw_n
{
direction = "input";
is_shared = "0";
type = "byteenable_n";
width = "4";
BOARD_COMPONENT altera_nios_dev_board_cyclone_2c35
{
component_pin = "U74.93,U74.94,U74.95,U74.96";
pin_assignment = "M3,M2,M4,M5";
}
}
PORT bwe_n
{
direction = "input";
is_shared = "0";
type = "write_n";
width = "1";
BOARD_COMPONENT altera_nios_dev_board_cyclone_2c35
{
component_pin = "U74.87";
pin_assignment = "J9";
}
}
PORT chipenable1_n
{
direction = "input";
is_shared = "0";
type = "chipselect_n";
width = "1";
BOARD_COMPONENT altera_nios_dev_board_cyclone_2c35
{
component_pin = "U74.98";
pin_assignment = "C7";
}
}
PORT clk
{
direction = "input";
is_shared = "1";
type = "clk";
width = "1";
visible = "0";
}
PORT data
{
direction = "inout";
is_shared = "0";
type = "data";
width = "32";
BOARD_COMPONENT altera_nios_dev_board_cyclone_2c35
{
component_pin = "U74.52,U74.53,U74.56,U74.57,U74.58,U74.59,U74.62,U74.63,U74.68,U74.69,U74.72,U74.73,U74.74,U74.75,U74.78,U74.79,U74.18,U74.19,U74.22,U74.23,U74.24,U74.25,U74.28,U74.29,U74.2,U74.3,U74.6,U74.7,U74.8,U74.9,U74.12,U74.13";
pin_assignment = "L2,L3,L7,L6,N9,P9,K1,K2,K4,K3,J2,J1,H2,H1,J3,J4,H3,H4,G1,G2,F2,F1,K8,K7,G4,G3,K6,K5,E2,E1,J8,J7";
}
}
PORT outputenable_n
{
direction = "input";
is_shared = "0";
type = "outputenable_n";
width = "1";
BOARD_COMPONENT altera_nios_dev_board_cyclone_2c35
{
component_pin = "U74.86";
pin_assignment = "D5";
}
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon_tristate";
Is_Memory_Device = "1";
Address_Alignment = "dynamic";
Data_Width = "32";
Address_Width = "19";
Has_IRQ = "0";
Read_Wait_States = "0";
Write_Wait_States = "0";
Read_Latency = "2";
Write_Latency = "0";
Setup_Time = "0";
Hold_Time = "0";
Active_CS_Through_Read_Latency = "1";
Base_Address = "0x02000000";
Address_Span = "2097152";
MASTERED_BY ext_ssram_bus/tristate_master
{
priority = "1";
}
Is_Base_Locked = "1";
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
}
}
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
Instantiate_In_System_Module = "0";
Default_Module_Name = "ssram";
Make_Memory_Model = "1";
View
{
MESSAGES
{
}
Is_Collapsed = "1";
}
Clock_Source = "clk_85";
Top_Level_Ports_Are_Enumerated = "1";
}
}
MODULE ext_flash_enet_bus
{
class = "altera_avalon_tri_state_bridge";
class_version = "2.0";
SLAVE avalon_slave
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Bridges_To = "tristate_master";
Base_Address = "N/A";
Has_IRQ = "0";
IRQ = "N/A";
Register_Outgoing_Signals = "1";
Register_Incoming_Signals = "1";
MASTERED_BY cpu/instruction_master
{
priority = "1";
}
MASTERED_BY cpu/data_master
{
priority = "1";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
}
}
MASTER tristate_master
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon_tristate";
Bridges_To = "avalon_slave";
}
}
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Is_Bridge = "1";
Clock_Source = "clk_85";
View
{
MESSAGES
{
}
Is_Collapsed = "1";
}
Top_Level_Ports_Are_Enumerated = "1";
}
}
MODULE ext_flash
{
class = "altera_avalon_cfi_flash";
class_version = "1.1";
iss_model_name = "altera_avalon_flash";
HDL_INFO
{
}
SLAVE s1
{
PORT_WIRING
{
PORT data
{
width = "8";
is_shared = "1";
direction = "inout";
type = "data";
BOARD_COMPONENT altera_nios_dev_board_cyclone_2c35
{
component_pin = "U5.35,U5.37,U5.39,U5.41,U5.44,U5.46,U5.48,U5.50";
pin_assignment = "D8,C8,F10,G10,D9,C9,B8,A8";
}
}
PORT address
{
width = "24";
is_shared = "1";
direction = "input";
type = "address";
BOARD_COMPONENT altera_nios_dev_board_cyclone_2c35
{
component_pin = "U5.51,U5.31,U5.26,U5.25,U5.24,U5.23,U5.22,U5.21,U5.20,U5.10,U5.9,U5.8,U5.7,U5.6,U5.5,U5.4,U5.3,U5.54,U5.19,U5.18,U5.11,U5.12,U5.15,U5.2";
pin_assignment = "F9,H8,D11,E8,B14,A14,F14,G14,F13,G13,C15,B15,B16,C16,D15,E15,H15,H16,A17,B17,G15,F15,F16,G16";
}
}
PORT read_n
{
width = "1";
is_shared = "0";
direction = "input";
type = "read_n";
BOARD_COMPONENT altera_nios_dev_board_cyclone_2c35
{
component_pin = "U5.34";
pin_assignment = "F17";
}
}
PORT write_n
{
width = "1";
is_shared = "0";
direction = "input";
type = "write_n";
BOARD_COMPONENT altera_nios_dev_board_cyclone_2c35
{
component_pin = "U5.13";
pin_assignment = "G17";
}
}
PORT select_n
{
width = "1";
is_shared = "0";
direction = "input";
type = "chipselect_n";
BOARD_COMPONENT altera_nios_dev_board_cyclone_2c35
{
component_pin = "U5.32";
pin_assignment = "H17";
}
}
}
WIZARD_SCRIPT_ARGUMENTS
{
class = "altera_avalon_cfi_flash";
Supports_Flash_File_System = "1";
flash_reference_designator = "U5";
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon_tristate";
Is_Nonvolatile_Storage = "1";
Is_Memory_Device = "1";
Address_Alignment = "dynamic";
Has_IRQ = "0";
Base_Address = "0x00000000";
Data_Width = "8";
Address_Width = "24";
Simulation_Num_Lanes = "1";
Convert_Xs_To_0 = "1";
Write_Wait_States = "160ns";
Read_Wait_States = "160ns";
Setup_Time = "45ns";
Hold_Time = "35ns";
Address_Span = "16777216";
MASTERED_BY ext_flash_enet_bus/tristate_master
{
priority = "1";
}
Is_Base_Locked = "1";
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
}
}
SYSTEM_BUILDER_INFO
{
Make_Memory_Model = "1";
Is_Enabled = "1";
Instantiate_In_System_Module = "0";
View
{
MESSAGES
{
}
Is_Collapsed = "1";
}
Clock_Source = "clk_85";
Top_Level_Ports_Are_Enumerated = "1";
}
WIZARD_SCRIPT_ARGUMENTS
{
Setup_Value = "45";
Wait_Value = "160";
Hold_Value = "35";
Timing_Units = "ns";
Unit_Multiplier = "1";
Size = "16777216";
MAKE
{
MACRO
{
EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX = "$(EXT_FLASH_FLASHTARGET_TMP1:0=)";
EXT_FLASH_FLASHTARGET_TMP1 = "$(ALT_SIM_OPTIMIZE:1=RUN_ON_HDL_SIMULATOR_ONLY_)";
}
MASTER cpu
{
MACRO
{
BOOT_COPIER = "boot_loader_cfi.srec";
CPU_CLASS = "altera_nios2";
CPU_RESET_ADDRESS = "0x0";
}
}
TARGET delete_placeholder_warning
{
ext_flash
{
Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
Is_Phony = "1";
Target_File = "do_delete_placeholder_warning";
}
}
TARGET factory
{
ext_flash
{
All_Depends_On = "0";
Command1 = "sof2flash --flash=U5 --offset=0xE00000 --output=factory.flash $(SOF) ";
Command2 = "nios2-flash-programmer --input=factory.flash --sof=$(shell $(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir altera_nios_dev_board_cyclone_2c35)/system/altera_nios_dev_board_cyclone_2c35.sof --device=1 $(JTAG_CABLE) --base=0x01000000 ";
Dependency = "";
Is_Phony = "1";
Target_File = "ext_flash_factory_configuration";
}
}
TARGET flashfiles
{
ext_flash
{
Command1 = "@echo Post-processing to create $(notdir $@)";
Command2 = "elf2flash --input=$(ELF) --flash=U5 --boot=$(shell $(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir $(CPU_CLASS))/$(BOOT_COPIER) --outfile=$(EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX)ext_flash.flash --sim_optimize=$(ALT_SIM_OPTIMIZE) --base=0x0 --end=0xFFFFFF --reset=$(CPU_RESET_ADDRESS) ";
Dependency = "$(ELF)";
Target_File = "$(EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX)ext_flash.flash";
}
}
TARGET programflash
{
ext_flash
{
All_Depends_On = "0";
Command1 = "nios2-flash-programmer --input=$(EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX)ext_flash.flash --sof=$(shell $(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir altera_nios_dev_board_cyclone_2c35)/system/altera_nios_dev_board_cyclone_2c35.sof --device=1 $(JTAG_CABLE) --base=0x01000000 ";
Dependency = "$(EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX)ext_flash.flash";
Is_Phony = "1";
Target_File = "ext_flash_programflash";
}
}
TARGET programflashnoelfdependency
{
ext_flash
{
All_Depends_On = "0";
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