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(text "SDRAM PLL" (rect 760 384 867 402)(font "Arial" (font_size 12)))
(text "This PLL introduces a phase-shift which compensates" (rect 760 408 1070 422)(font "Arial" (font_size 8)))
(text "for board-level delays in the clock network.  Other boards" (rect 760 424 1089 438)(font "Arial" (font_size 8)))
(text "may require different settings." (rect 760 440 931 454)(font "Arial" (font_size 8)))
(text "Double-click symbol to edit system with SOPC-Builder" (rect 768 536 1209 554)(font "Arial" (color 0 0 0)(font_size 12)))
(text "This design is an excellent starting-point for Nios systems built" (rect 152 144 506 158)(font "Arial" (color 0 0 0)(font_size 8)))
(text "Targeted for Nios kit Stratix II 2S60ES development board." (rect 152 216 515 231)(font "Times New Roman" (color 0 0 0)(font_size 10)))
(text "standard -- Nios II, Stratix II 2S60ES" (rect 152 112 606 139)(font "Arial" (color 0 0 0)(font_size 18)))
(text "on the Stratix II 2S60ES Development Board. It contains a Nios II /s core" (rect 152 160 554 174)(font "Arial" (color 0 0 0)(font_size 8)))
(text "and peripherals to interface to most components on the development" (rect 152 176 541 190)(font "Arial" (color 0 0 0)(font_size 8)))
(text "board." (rect 152 192 188 206)(font "Arial" (color 0 0 0)(font_size 8)))
(text "Quartus II.  If you wish to get the maximum FMAX performance out of the Nios II" (rect 544 144 993 158)(font "Arial" (color 0 128 0)(font_size 8)))
(text "standard design, it is recommended that you enable the following Physical" (rect 544 160 964 174)(font "Arial" (color 0 128 0)(font_size 8)))
(text "Synthesis settings in Quartus II." (rect 544 176 723 190)(font "Arial" (color 0 128 0)(font_size 8)))
(text "Be aware these settings may significantly affect Quartus II compile time." (rect 544 240 953 254)(font "Arial" (color 0 128 0)(font_size 8)))
(text "For help making these settings, please consult Quartus II Online Help." (rect 544 256 934 270)(font "Arial" (color 0 128 0)(font_size 8)))
(text "- Perform physical synthesis for combinational logic" (rect 552 192 890 205)(font "Arial" (color 0 128 0)(font_size 8)(bold_italic)))
(text "- Perform register duplication" (rect 552 208 745 221)(font "Arial" (color 0 128 0)(font_size 8)(bold_italic)))
(text "- Perform register retiming" (rect 552 224 725 237)(font "Arial" (color 0 128 0)(font_size 8)(bold_italic)))
(text "By default, this standard example design project is configured to always" (rect 544 112 955 126)(font "Arial" (color 0 128 0)(font_size 8)))
(text "achieve an FMAX of at least 50MHz, yet provide a relatively quick compile in" (rect 544 128 974 142)(font "Arial" (color 0 128 0)(font_size 8)))
(text "E-net used in asynch mode." (rect 1280 568 1428 582)(font "Times New Roman" (color 0 0 0)(font_size 8)))
(text "is generated by CPLD reset distribution logic." (rect 1504 744 1757 758)(font "Arial" (font_size 8)))
(text "Note: Compact Flash reset_n on Nios Development Boards" (rect 1504 728 1835 742)(font "Arial" (font_size 8)))