?? std_2s60es.ptf
字號(hào):
}
}
PORT write_n
{
width = "1";
is_shared = "0";
direction = "input";
type = "write_n";
BOARD_COMPONENT altera_nios_dev_board_stratix_2s60_es
{
component_pin = "U35.17";
pin_assignment = "J21";
}
}
PORT be_n
{
width = "4";
is_shared = "0";
direction = "input";
type = "byteenable_n";
BOARD_COMPONENT altera_nios_dev_board_stratix_2s60_es
{
component_pin = "U35.39,U35.40,U36.39,U36.40";
pin_assignment = "K20,K19,K22,K21";
}
}
PORT select_n
{
width = "1";
is_shared = "0";
direction = "input";
type = "chipselect_n";
BOARD_COMPONENT altera_nios_dev_board_stratix_2s60_es
{
component_pin = "U35.6";
pin_assignment = "J19";
}
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon_tristate";
Is_Memory_Device = "1";
Address_Alignment = "dynamic";
Data_Width = "32";
Address_Width = "18";
Has_IRQ = "0";
Read_Wait_States = "0ns";
Write_Wait_States = "0ns";
Hold_Time = "half";
Base_Address = "0x02000000";
Address_Span = "1048576";
MASTERED_BY ext_ram_bus/tristate_master
{
priority = "1";
}
Setup_Time = "0";
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
Is_Base_Locked = "1";
}
}
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
Instantiate_In_System_Module = "0";
Make_Memory_Model = "1";
Default_Module_Name = "sram";
View
{
MESSAGES
{
}
Is_Collapsed = "1";
}
Clock_Source = "clk";
Top_Level_Ports_Are_Enumerated = "1";
}
}
MODULE onchip_ram_64_kbytes
{
class = "altera_avalon_onchip_memory2";
class_version = "5.0";
iss_model_name = "altera_memory";
HDL_INFO
{
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/onchip_ram_64_kbytes.v";
Precompiled_Simulation_Library_Files = "";
Synthesis_Only_Files = "";
}
WIZARD_SCRIPT_ARGUMENTS
{
allow_mram_sim_contents_only_file = "0";
ram_block_type = "M4K";
gui_ram_block_type = "M4K";
Writeable = "1";
dual_port = "0";
Size_Value = "64";
Size_Multiple = "1024";
contents_info = "QUARTUS_PROJECT_DIR/onchip_ram_64_kbytes.hex 1114053455 ";
MAKE
{
TARGET delete_placeholder_warning
{
onchip_ram_64_kbytes
{
Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
Is_Phony = "1";
Target_File = "do_delete_placeholder_warning";
}
}
TARGET hex
{
onchip_ram_64_kbytes
{
Command1 = "@echo Post-processing to create $(notdir $@)";
Command2 = "elf2hex $(ELF) 0x02100000 0x210FFFF --width=32 $(QUARTUS_PROJECT_DIR)/onchip_ram_64_kbytes.hex --create-lanes=0";
Dependency = "$(ELF)";
Target_File = "$(QUARTUS_PROJECT_DIR)/onchip_ram_64_kbytes.hex";
}
}
TARGET sim
{
onchip_ram_64_kbytes
{
Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";
Command3 = "touch $(SIMDIR)/dummy_file";
Dependency = "$(ELF)";
Target_File = "$(SIMDIR)/dummy_file";
}
}
}
}
SYSTEM_BUILDER_INFO
{
Prohibited_Device_Family = "MERCURY, APEX20K, APEX20KE, APEX20KC, APEXII, ACEX1K, FLEX10KE, EXCALIBUR_ARM, MAXII";
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Default_Module_Name = "onchip_memory";
View
{
MESSAGES
{
}
Is_Collapsed = "1";
}
Clock_Source = "clk";
Top_Level_Ports_Are_Enumerated = "1";
}
SLAVE s1
{
PORT_WIRING
{
PORT address
{
direction = "input";
type = "address";
width = "14";
Is_Enabled = "1";
}
PORT byteenable
{
direction = "input";
type = "byteenable";
width = "4";
Is_Enabled = "1";
}
PORT chipselect
{
direction = "input";
type = "chipselect";
width = "1";
Is_Enabled = "1";
}
PORT clk
{
direction = "input";
type = "clk";
width = "1";
Is_Enabled = "1";
}
PORT readdata
{
direction = "output";
type = "readdata";
width = "32";
Is_Enabled = "1";
}
PORT write
{
direction = "input";
type = "write";
width = "1";
Is_Enabled = "1";
}
PORT writedata
{
direction = "input";
type = "writedata";
width = "32";
Is_Enabled = "1";
}
PORT clken
{
default_value = "1'b1";
direction = "input";
type = "clken";
width = "1";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Memory_Device = "1";
Address_Alignment = "dynamic";
Address_Width = "14";
Data_Width = "32";
Has_IRQ = "0";
Read_Wait_States = "0";
Write_Wait_States = "0";
Address_Span = "65536";
Read_Latency = "1";
Base_Address = "0x02100000";
MASTERED_BY cpu/instruction_master
{
priority = "1";
}
MASTERED_BY cpu/data_master
{
priority = "1";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
Is_Base_Locked = "1";
Is_Channel = "1";
Is_Writable = "1";
}
}
SLAVE s2
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Memory_Device = "1";
Address_Alignment = "dynamic";
Address_Width = "14";
Data_Width = "32";
Has_IRQ = "0";
Read_Wait_States = "0";
Write_Wait_States = "0";
Address_Span = "65536";
Read_Latency = "1";
Is_Enabled = "0";
Is_Channel = "1";
Is_Writable = "1";
}
}
SIMULATION
{
DISPLAY
{
SIGNAL a
{
name = "chipselect";
conditional = "1";
}
SIGNAL b
{
name = "write";
conditional = "1";
}
SIGNAL c
{
name = "address";
radix = "hexadecimal";
}
SIGNAL d
{
name = "byteenable";
radix = "binary";
conditional = "1";
}
SIGNAL e
{
name = "readdata";
radix = "hexadecimal";
}
SIGNAL f
{
name = "writedata";
radix = "hexadecimal";
conditional = "1";
}
}
}
PORT_WIRING
{
}
}
MODULE lan91c111
{
class = "altera_avalon_lan91c111";
class_version = "2.3";
WIZARD_SCRIPT_ARGUMENTS
{
CONSTANTS
{
CONSTANT LAN91C111_REGISTERS_OFFSET
{
value = "0x0300";
comment = "offset 0 or 0x300, depending on address bus wiring";
}
CONSTANT LAN91C111_DATA_BUS_WIDTH
{
value = "32";
comment = "width 16 or 32, depending on data bus wiring";
}
}
Is_Ethernet_Mac = "1";
}
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "0";
Wire_Test_Bench_Values = "1";
Is_Enabled = "1";
View
{
MESSAGES
{
}
Is_Collapsed = "1";
}
Clock_Source = "clk";
Top_Level_Ports_Are_Enumerated = "1";
}
SLAVE s1
{
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "0";
Is_Enabled = "1";
Is_Bus_Master = "0";
Bus_Type = "avalon_tristate";
Uses_Tri_State_Data_Bus = "1";
Address_Alignment = "native";
Address_Width = "14";
Data_Width = "32";
Has_IRQ = "1";
Read_Wait_States = "20ns";
Write_Wait_States = "20ns";
Setup_Time = "20ns";
Hold_Time = "20ns";
Is_Memory_Device = "0";
Date_Modified = "2002.03.19.10:51:51";
Base_Address = "0x02110000";
Tri_State_Data_Bus = "--unknown--";
MASTERED_BY ext_ram_bus/tristate_master
{
priority = "1";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "6";
}
}
PORT_WIRING
{
PORT irq
{
direction = "output";
width = "1";
type = "irq";
test_bench_value = "0";
is_shared = "0";
BOARD_COMPONENT altera_nios_dev_board_stratix_2s60_es
{
component_pin = "U4.29";
pin_assignment = "AD11";
}
}
PORT byteenablen
{
is_shared = "0";
direction = "input";
width = "4";
type = "byteenable_n";
BOARD_COMPONENT altera_nios_dev_board_stratix_2s60_es
{
component_pin = "U4.94,U4.95,U4.96,U4.97";
pin_assignment = "AD8,AF9,Y11,W12";
}
}
PORT address
{
is_shared = "1";
direction = "input";
width = "14";
type = "address";
lsb = "2";
BOARD_COMPONENT altera_nios_dev_board_stratix_2s60_es
{
component_pin = "U4.79,U4.80,U4.81,U4.82,U4.83,U4.84,U4.85,U4.86,U4.87,U4.88,U4.89,U4.90,U4.91,U4.92";
pin_assignment = "U1,U2,V1,V2,W1,W2,Y1,Y2,AA1,AA2,AB1,AB2,W3,W4";
}
}
PORT data
{
is_shared = "1";
direction = "inout";
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