library verilog;use verilog.vl_types.all;entity pwm_main is    port(        up              : in     vl_logic;        dn              : in     vl_logic;        pwm             : out    vl_logic;        pwm_inv         : out    vl_logic;        pwm1            : out    vl_logic;        pwm2            : out    vl_logic;        pwm3            : out    vl_logic;        pwm4            : out    vl_logic    );end pwm_main;