Version 7.2 Build 151 09/26/2007 SJ Full Version
39
2318
OFF
OFF
OFF
OFF
ON
ON
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
pwm_main
# storage
db|pwm_main.(0).cnf
db|pwm_main.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
pwm_main.v
56cc1d8538856aaf269e3b2f746dec93
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# hierarchies {
|
}
# lmf
v:|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
altufm_osc0_altufm_osc_1p3
# storage
db|pwm_main.(1).cnf
db|pwm_main.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
pwm_main.v
56cc1d8538856aaf269e3b2f746dec93
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# memory_file {
none
0
}
# hierarchies {
altufm_osc0_altufm_osc_1p3:u1
}
# lmf
v:|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
clk_gen
# storage
db|pwm_main.(2).cnf
db|pwm_main.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
pwm_main.v
56cc1d8538856aaf269e3b2f746dec93
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# hierarchies {
clk_gen:u2
}
# lmf
v:|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
duty_cycle
# storage
db|pwm_main.(3).cnf
db|pwm_main.(3).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
pwm_main.v
56cc1d8538856aaf269e3b2f746dec93
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# hierarchies {
duty_cycle:u3
}
# lmf
v:|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
pwm_gen
# storage
db|pwm_main.(4).cnf
db|pwm_main.(4).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
pwm_main.v
56cc1d8538856aaf269e3b2f746dec93
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# hierarchies {
pwm_gen:u4
}
# lmf
v:|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# complete