{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 05 10:41:35 2007 " "Info: Processing started: Mon Nov 05 10:41:35 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off pwm_main -c pwm_main " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off pwm_main -c pwm_main" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clk_gen:u2\|duty_cycle_clk " "Info: Detected ripple clock \"clk_gen:u2\|duty_cycle_clk\" as buffer" {  } { { "pwm_main.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/quartus/pwm_main.v" 97 -1 0 } } { "v:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "v:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_gen:u2\|duty_cycle_clk" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clk_gen:u2\|pwm_clk " "Info: Detected ripple clock \"clk_gen:u2\|pwm_clk\" as buffer" {  } { { "pwm_main.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/quartus/pwm_main.v" 97 -1 0 } } { "v:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "v:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_gen:u2\|pwm_clk" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Warning" "WTAN_NOTHING_TO_TIMING_ANALYZE" "" "Warning: No paths found for timing analysis" {  } {  } 0 0 "No paths found for timing analysis" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "115 " "Info: Allocated 115 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 05 10:41:38 2007 " "Info: Processing ended: Mon Nov 05 10:41:38 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}