module BarkerCodeDecision (Clock50MHz,RST,SampleCLK,DatafromSRC,BarkerFlag);	input  Clock50MHz;	input  RST;		input  SampleCLK;	input  [12:0] DatafromSRC;	output BarkerFlag;	parameter S_WaitforAdder	= 4'b0001; // wait for the Adder to be valid	parameter S_DotheAddition	= 4'b0010; // do the addition operation			parameter S_BarkerDecision	= 4'b0100; // decide the Barker Code	parameter S_IDLE			= 4'b1000; // idle		parameter BARKERCODE		= 13'b1_1111_0011_0101;	wire [12:0] Adder;	reg SampleVofSCLKLT	= 1'b0; // Last Time sample value of the Sample Clock 	reg SampleVofSCLKCT	= 1'b0; // Current Time sample value of the Sample Clock 	reg BarkerFlag 		= 1'b0;	reg [3:0] AddResult	= 4'b0000;	reg [3:0] StateofBCD;		assign Adder[0]		= DatafromSRC[0] ^~ 1'b1; 	assign Adder[1]		= DatafromSRC[1] ^~ 1'b0;	assign Adder[2]		= DatafromSRC[2] ^~ 1'b1;	assign Adder[3]		= DatafromSRC[3] ^~ 1'b0;	assign Adder[4]		= DatafromSRC[4] ^~ 1'b1;	assign Adder[5]		= DatafromSRC[5] ^~ 1'b1;	assign Adder[6]		= DatafromSRC[6] ^~ 1'b0;	assign Adder[7]		= DatafromSRC[7] ^~ 1'b0;	assign Adder[8]		= DatafromSRC[8] ^~ 1'b1;	assign Adder[9]		= DatafromSRC[9] ^~ 1'b1;	assign Adder[10]	= DatafromSRC[10] ^~ 1'b1;	assign Adder[11]	= DatafromSRC[11] ^~ 1'b1;	assign Adder[12]	= DatafromSRC[12] ^~ 1'b1;	always@(posedge Clock50MHz)	begin		SampleVofSCLKCT	<= SampleCLK;		SampleVofSCLKLT	<= SampleVofSCLKCT;	end		always@(posedge Clock50MHz)	begin		case(StateofBCD)			S_WaitforAdder:			begin				if(RST == 1'b0)				begin					StateofBCD	<= S_IDLE;				end				else				begin					StateofBCD	<= S_DotheAddition;				end			end			S_DotheAddition:			begin				if(RST == 1'b0)				begin					StateofBCD	<= S_IDLE;				end				else				begin					StateofBCD	<= S_BarkerDecision;				end			end			S_BarkerDecision:			begin				StateofBCD	<= S_IDLE;			end			S_IDLE:			begin				if({SampleVofSCLKLT,SampleVofSCLKCT} == 2'b01)				begin					StateofBCD	<= S_WaitforAdder;				end				else				begin					StateofBCD	<= S_IDLE;				end			end			default:			begin				StateofBCD		<= S_IDLE;			end		endcase	end		always@(posedge Clock50MHz)	begin		case(StateofBCD)			S_DotheAddition:			begin				AddResult		<= Adder[0] + Adder[1] + Adder[2] + Adder[3] +								   Adder[4] + Adder[5] + Adder[6] + Adder[7] +								   Adder[8] + Adder[9] + Adder[10] + Adder[11] +								   Adder[12];			end			S_BarkerDecision:			begin				if(AddResult > 4'b1011)				begin					BarkerFlag	<= 1'b1;				end				else				begin					BarkerFlag	<= 1'b0;				end			end		endcase	endendmodule