`timescale 1ns/100psmodule ShiftRegController (Clock50MHz,BitStreamIn,SampleCLKfromDM,SampleCLK,DataOut);	input  Clock50MHz;	input  BitStreamIn;	input  SampleCLKfromDM;		output SampleCLK;	output [31:0] DataOut;		reg [2:0] SampleCLKCONT;	reg [31:0] DataOut;	reg SampleCLK;	reg [1:0] DPSKReg;		always@(posedge Clock50MHz)	begin		if(SampleCLKfromDM == 1'b0)		begin			SampleCLKCONT	<= 3'b000;		end		else if(SampleCLKCONT == 3'b111)		begin			SampleCLKCONT	<= 3'b111;		end		else		begin			SampleCLKCONT	<= SampleCLKCONT + 1'b1;		end	end		always@(posedge Clock50MHz)	begin		if(SampleCLKCONT == 3'b101)		begin			DPSKReg	<= {DPSKReg[0],BitStreamIn};		end		else		begin			DPSKReg	<= DPSKReg;		end	end		always@(posedge Clock50MHz)	begin		if((SampleCLKCONT == 3'b110) && (DPSKReg == 2'b00))		begin			DataOut <= {DataOut[30:0],1'b1};		end		else if((SampleCLKCONT == 3'b110) && (DPSKReg == 2'b11))		begin			DataOut <= {DataOut[30:0],1'b1};		end		else if((SampleCLKCONT == 3'b110) && (DPSKReg == 2'b01))		begin			DataOut <= {DataOut[30:0],1'b0};		end		else if((SampleCLKCONT == 3'b110) && (DPSKReg == 2'b10))		begin			DataOut <= {DataOut[30:0],1'b0};		end		end		always@(posedge Clock50MHz)	begin		if(SampleCLKCONT == 3'b111)		begin			SampleCLK 	<= 1'b1;		end		else		begin			SampleCLK 	<= 1'b0;		end	end	endmodule