library verilog;use verilog.vl_types.all;entity EndFlagDecision is    generic(        S_WaitforCMPResValid: integer := 1;        S_DotheComparation: integer := 2;        S_IDLE          : integer := 4;        TAILFLAG        : integer := 441    );    port(        Clock50MHz      : in     vl_logic;        RST             : in     vl_logic;        SampleCLK       : in     vl_logic;        DatafromSRC     : in     vl_logic_vector(31 downto 0);        EndFlag         : out    vl_logic    );end EndFlagDecision;