// 編寫時(shí)間: 2008.01.05// 最后更新: 2008.01.06// 編寫人員: 梁浩// 版本編號(hào): V1.0// 功能描述: 該模塊實(shí)現(xiàn)了系統(tǒng)控制器`timescale 1ns/100psmodule TotalSystemController (Clock50MHz,SampleCLK,RST,							  BarkerFlag,TailFlag,							  SPICONTRST,S_WforH_Flag);	input  Clock50MHz;	input  SampleCLK;	input  RST;	input  BarkerFlag;	input  TailFlag;	output SPICONTRST;	output S_WforH_Flag;		parameter S_RST					= 9'b0_0000_0001;	parameter S_WaitforHead 		= 9'b0_0000_0010;	parameter S_ShiftRegBusy		= 9'b0_0000_0100;	parameter S_Delay01				= 9'b0_0000_1000;	parameter S_ShiftCONTDecision	= 9'b0_0001_0000;	parameter S_ShiftCONTAdd		= 9'b0_0010_0000;	parameter S_TailDecision		= 9'b0_0100_0000;	parameter S_SPIStart			= 9'b0_1000_0000;	parameter S_IDLE				= 9'b1_0000_0000;	reg SPICONTRST;		reg [8:0] StateofTSC;	reg [4:0] ShiftCONT		= 5'b0_0000;	reg SampleVofSCLKLT		= 1'b0;	reg SampleVofSCLKCT		= 1'b0;		reg S_WforH_Flag;		wire ShiftCONTFullFlag;		assign ShiftCONTFullFlag	= ShiftCONT[0] && ShiftCONT[1] && ShiftCONT[2] && ShiftCONT[3] && ShiftCONT[4];		always@(posedge Clock50MHz)	begin		SampleVofSCLKCT	<= SampleCLK;		SampleVofSCLKLT	<= SampleVofSCLKCT;	end	always@(posedge Clock50MHz)	begin		case(StateofTSC)			S_RST:			begin				if(RST == 1'b1)				begin					StateofTSC	<= S_WaitforHead;				end				else				begin					StateofTSC	<= S_RST;				end			end			S_WaitforHead:			begin				if(RST == 1'b0)				begin					StateofTSC	<= S_RST;				end				else if(BarkerFlag == 1'b1)				begin					StateofTSC	<= S_IDLE;				end				else				begin					StateofTSC	<= S_WaitforHead;				end			end			S_ShiftRegBusy:			begin				if(RST == 1'b0)				begin					StateofTSC	<= S_RST;				end				else				begin					StateofTSC	<= S_Delay01;				end			end			S_Delay01:			begin				if(RST == 1'b0)				begin					StateofTSC	<= S_RST;				end				else				begin					StateofTSC	<= S_ShiftCONTDecision;				end			end			S_ShiftCONTDecision:			begin				if(RST == 1'b0)				begin					StateofTSC	<= S_RST;				end				else if(ShiftCONTFullFlag == 1'b1)				begin					StateofTSC	<= S_TailDecision;				end				else				begin					StateofTSC	<= S_ShiftCONTAdd;				end			end			S_TailDecision:			begin				if(RST == 1'b0)				begin					StateofTSC	<= S_RST;				end				else if(TailFlag == 1'b1)				begin					StateofTSC	<= S_WaitforHead;				end				else				begin					StateofTSC	<= S_SPIStart;				end			end			S_SPIStart:			begin				if(RST == 1'b0)				begin					StateofTSC	<= S_RST;				end				else				begin					StateofTSC	<= S_IDLE;				end			end			S_ShiftCONTAdd:			begin				if(RST == 1'b0)				begin					StateofTSC	<= S_RST;				end				else				begin					StateofTSC	<= S_IDLE;				end			end			S_IDLE:			begin				if(RST == 1'b0)				begin					StateofTSC	<= S_RST;				end				else if({SampleVofSCLKLT,SampleVofSCLKCT} == 2'b01)				begin					StateofTSC	<= S_ShiftRegBusy;				end				else				begin					StateofTSC	<= S_IDLE;				end			end			default:			begin				StateofTSC		<= S_IDLE;			end		endcase	end		always@(posedge Clock50MHz)	begin		case(StateofTSC)			S_RST:			begin				SPICONTRST		<= 1'b1;				ShiftCONT		<= 5'b0_0000;				S_WforH_Flag	<= 1'b0;			end			S_WaitforHead:			begin				SPICONTRST		<= 1'b1;				ShiftCONT		<= 5'b0_0000;				S_WforH_Flag	<= 1'b1;			end			S_ShiftRegBusy:			begin				SPICONTRST		<= 1'b1;			end			S_SPIStart:			begin				SPICONTRST		<= 1'b0;				ShiftCONT		<= 5'b0_0000;			end			S_ShiftCONTAdd:			begin				ShiftCONT		<= ShiftCONT + 1'b1;			end			S_IDLE:			begin				S_WforH_Flag	<= 1'b0;			end		endcase	endendmodule