// 編寫時(shí)間: 2008.01.05// 最后更新: 2008.01.05// 編寫人員: 梁浩// 版本編號: V1.0// 功能描述: 該模塊實(shí)現(xiàn)了FPGA上電后的自復(fù)位脈沖`timescale 1ns / 100psmodule RSTGenerator (Clock50MHz,RSTCMP,RST);	output RSTCMP;		// system reset compare	output RST;			// system reset	input  Clock50MHz;	// system clock 50MHz		reg RSTCMP;	reg RST;		// used in the practice	//reg [23:0] CONTRST = 24'b0000_0000_0000_0000_0000_0000;	//always@(posedge Clock50MHz)	//begin	//	if(CONTRST == 24'b1111_1111_1111_1111_1111_1111)	//	begin	//		CONTRST	<= CONTRST;	//		RSTCMP	<= 1'b1;	//		RST		<= 1'b1;	//	end	//	else	//	begin	//		CONTRST	<= CONTRST + 1'b1;	//		RSTCMP	<= 1'b1;	//		RST		<= 1'b0;	//	end	//end	// used in the simulation	reg [3:0] CONTRST = 4'b0000;	always@(posedge Clock50MHz)	begin		if(CONTRST == 4'b1111)		begin			CONTRST	<= CONTRST;			RSTCMP	<= 1'b1;			RST		<= 1'b1;		end		else		begin			CONTRST	<= CONTRST + 1'b1;			RSTCMP	<= 1'b1;			RST		<= 1'b0;		end	end	endmodule