library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity mux2_1 is
generic(n:integer:=24);	
port(
	sel:in bit;
	A,B:in std_logic;
	Y:out std_logic);
end mux2_1;
architecture behave of mux2_1 is
	signal data:std_logic;
	begin
		with sel select
		     data<=A when '1',
		     	   B when '0';
		Y<=data;
	end behave;